Claims
- 1. A method of forming an interconnect line in an insulator layer of a semiconductor structure, said method comprising:
- forming an insulator layer;
- forming a trench in said insulator layer, said trench having a first depth within said insulator layer for an interconnect line and a second depth through said insulator layer for contact of said interconnect line to a layer underlying said insulator layer;
- forming a pattern of sections of material transversely and spaced apart within said trench;
- forming a layer of diffusion barrier material over said pattern and within said trench;
- removing a portion of said diffusion barrier material so as to form a plurality of transverse spaced apart vertical sections of diffusion barrier material within said trench;
- removing said pattern of material, so as to leave a plurality of transverse diffusion barriers spaced apart within said trench; and
- forming a layer of metallization within remaining portions of said trench, said metallization and said plurality of transverse diffusion barriers thereby forming an interconnect line within said insulator layer wherein said interconnect line has a plurality of transverse diffusion barriers spaced apart therein.
- 2. The method of claim 1 wherein said sections of said pattern are spaced apart in the range of 20-50 microns.
- 3. The method of claim 1 wherein said sections of said pattern are spaced apart in the range of 0.4 to 0.8 microns.
- 4. The method of claim 1 wherein one of said plurality of transverse diffusion barriers overlies said trench at said second depth and comprises a stud for connecting said interconnect line to a layer underlying said insulator layer.
- 5. The method of claim 1 further comprising planarizing said interconnect line and said plurality of transverse diffusion barriers to a level of said insulator layer.
Parent Case Info
This application is a division of application Ser. No. 08/169,787, filed Dec. 20, 1993.
US Referenced Citations (3)
Non-Patent Literature Citations (1)
Entry |
W. Buthrie et al, IBM Tech. Discl. Bull., 32 (10B), pp. 114-115 1990. |
Divisions (1)
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Number |
Date |
Country |
Parent |
169787 |
Dec 1993 |
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