Patent Grant
9490072
The present invention is related to a capacitor exhibiting high capacitance per unit volume. More specifically, the present invention is related to an improved conductive inner electrode design which improves electrode overlap, and therefore capacitance, with high voltage rating and no arc-over.
Traditional high voltage capacitor designs, such as for use at ≧500Vdc, typically combine 2 or more capacitors in series within the same multilayer ceramic device package. These serial designs are effective at increasing effective voltage since the effective voltage is divided between the 2 capacitors. Capacitors arranged in series are also effective in decreasing the occurrence of surface-arc-over. Unfortunately, the effective capacitance, Ceff, of a serial device is significantly lowered since 1/Ceff=Σ1/Cn where n is the number of capacitors in series.
The practitioner has therefore had to balance the desire for high voltage capability, which can be improved by serial capacitors, with the desire for high capacitance, which is compromised with serial capacitors.
For voltages up to about 2,500 Vdc the capacitance can be increased with minimal flash over by coating the capacitors themselves, or the board or assembled device, using standard MLCC designs. In the case of the individual monolithic multilayer capacitors the leads are attached and the part epoxy coated. A significant disadvantage to this approach is that the leaded part cannot typically be used in an automated surface mount assembly process and there is some additional cost associated with the leads and epoxy.
One approach to mitigate the problem associated with flashover is described in U.S. Pat. No. 6,134,098 wherein lower K dielectric layers are used on the top and bottom of a series capacitor design. Although this approach is effective to decrease flash over this is still a serial capacitor design and the effective capacitance is lower as detailed above. Furthermore, differences in the thermal expansion coefficient of the various materials are problematic since thermal stresses are created during tiring.
Japanese Patent Abstract 2006-066831 by SHIMIZU MICHINAO, ITO KAZUNORI and KOMATSU TOSHIAKI discloses a multilayer ceramic capacitor design which raises the starting voltage of the surface discharge. To achieve this effect a serial type arrangement of capacitors, using multiple internal electrode prints, is required.
Coating of parts whilst retaining the ability to surface mount can retard arc over. U.S. Pat. No. 6,627,529, by Duva and related U.S. Pat. No. 6,683,782, both of which are incorporated herein by reference, describe the benefits, and method, for applying para-xylylene polymer coatings to multi-layer ceramic capacitors. Coating individual parts, or the final assemblies, is cost prohibitive so these approaches have been restricted to high value added applications in electronics.
Capacitance, C, is defined by the following equation; C=∈r∈0An/t; where ∈r is the relative permittivity of the dielectric; ∈0 is a constant equal to the permittivity of free space; A is the overlap area for each internal conductive layer, also referred to as an active; n is the number of actives and t is the separation distance or thickness between the electrodes. Therefore, it is an ongoing desire to increase the number of layers and overlap area while decreasing the layer separation. Often the efforts to increase voltage are contrary to one, or more of these desires.
For example, in a more recent approach presented in U.S. Pat. No. 7,336,475 by Bultitude et al, which is incorporated herein by reference, shield electrodes are used which allow for a high voltage capability by prohibiting surface-arc-over whilst retaining a relatively high overlap area for high capacitance in a non-serial design. This design combines a top and bottom shield electrode that protects the oppositely charged electrode below from arc-over from the terminal in contact with the shield. Side shields are also described which function in a similar manner by protecting each active electrode along the side of the part by connecting to the terminal of opposite polarity while overlapping the active electrode to prevent arc over.
US Pat. Publ. No. 2009/0052111 also to Bultitude, the entirety of which is incorporated by reference, describes the use of a coating of polyimide applied by spin coating to further increase voltage breakdown. Related US Pat. Publ. No. 2009/0052112, the entirety of which is incorporated by reference, describes the need to shield between the terminal and the opposed electrode. In both cases the MLCC designs described use side shields connected to the opposed terminal.
The presence of side shields connected to the opposite terminal in each of the active layers confers a risk of a breakdown pathway between the shields and the active electrode. This pathway may occur due to contamination or electrode “bleed out” during the electrode printing process that would result in a short circuit and catastrophic failure of the capacitor. Furthermore, although the prior art designs have more overlap, and therefore higher capacitance, than the serial designs the side shields take-up a significant area which does not contribute to capacitance. The area occupied by the side shields decreases the available capacitance as a function of total volume since the area occupied by the shields can not be utilized for electrode overlap.
In spite of the advances in the art there is still a long standing desire for a capacitor with improved capacitance, for use in high voltage applications, which has minimal flashover. Such a capacitor is provided herein.
It is an object of this invention to provide a capacitor with reduced flashover, also called surface-arc-over, without the need for another type of dielectric with potential thermal mismatch issues between different dielectrics whilst maintaining a high capacitance.
It is another object of the invention to provide a capacitor with improved capacitance, per unit volume, without loss of effective voltage rating and with decreased flashover.
These and other inventions, as will be realized an improved capacitor. The capacitor has first internal conductors and second internal conductors in an alternating layer wherein the first internal conductor has a first polarity and the second internal conductor has opposing polarity. A first external termination is in electrical contact with the first internal conductors wherein the first external termination has a first side extension which extends a distance along a side of the capacitor which is perpendicular to the first internal conductors and the second internal conductors. A second external termination is in electrical contact with the second internal conductors wherein the second external termination has a second side extension which extends a second distance along a second side of the capacitor which is perpendicular to the first internal conductors and the second internal conductors. The first internal conductors extend towards the second external termination to a separation distance from the second external termination which is less than the second distance. The first internal conductors comprise a bulk region and a secondary region wherein the secondary region has a region width which is less than a bulk width of the bulk region.
Yet another embodiment is provided in an improved capacitor. The capacitor has first internal conductors and second internal conductors in an alternating layer wherein the first internal conductor has a first polarity and the second internal conductor has opposing polarity. A first external termination is in electrical contact with the first internal conductors wherein the first external termination has a first side extension which extends a distance along a side of the capacitor which is perpendicular to the first internal conductors and the second internal conductors. A second external termination is in electrical contact with the second internal conductors wherein the second external termination has a second side extension which extends a second distance along a second side of the capacitor which is perpendicular to the first internal conductors and the second internal conductors. The first internal conductors extend towards the second external termination to a separation distance from the second external termination which is less than the second distance. The first internal conductors comprise a bulk region and a secondary region wherein the secondary region is further from the second side extension than the second distance.
Yet another embodiment is provided in a method of forming an multilayered ceramic capacitor. The method includes the steps of:
The present invention is directed to an improved capacitor. More specifically, the present invention is directed to a capacitor with improved geometry of inner conductive layers.
The invention will be described with reference to the various figures which are an integral non-limiting component of the disclosure. Throughout the figures similar elements will be numbered accordingly. For simplicity, a minimal number of active layers is illustrated with the understanding that the actual number used may be quite large.
A cross-sectional schematic view of a multi-layer ceramic capacitor of the present invention is illustrated schematically in
A cross-sectional schematic view of the capacitor of
An embodiment of the invention is illustrated in cross-sectional schematic view taken parallel to the inner electrodes in
For the purposes of discussion the first conductive inner electrode and second conductive inner electrode are of the same shape and size. Different shapes and sizes are functional yet for manufacturing purposes it is highly desirable that they be the same since each is designed to be as large as possible within the constraints of avoiding flashover as will be more fully described. In the discussion, conductive inner electrode will refer to one layer or both layers.
The inner conductive layer is defined as having a bulk zone, 120, which is most preferably rectangular, and a secondary zone, 121. The bulk zone and secondary zone are defined for the purposes of geometry and taken together they form a seamless inner conductive layer preferably with no difference in layer thickness or composition. At least a portion of the secondary zone is a distance, D1, from the external termination of opposing polarity and a distance, D2, is the distance the external termination side extension, 117, extends along the side away from the external termination to avoid a close point of approach between 118 and 117.
The bulk zone, 120, preferably is as large as possible to provide the most overlap with the inner conductive layer of opposing polarity. The secondary zone, 121, comprises a region which has a width which is narrower than the width, W, of the bulk zone. The narrowed region of the secondary zone insures that the closest distance between the external termination side extension, 117, and the narrowed portion, 118, of the secondary zone is at least as large as the closest separation distance between the conductive inner electrode and external termination of opposing polarity, represented as D1. The height of the bulk zone, H, is preferably at least 66% of the longest length of the inner conductive layer measured from the contact point with the exterior termination of common polarity. A height of the bulk zone of as low as 25% has been demonstrated successfully.
Representative conductive inner electrodes are illustrated schematically in
In
In
In
In
In
In
In the secondary zone the radius of any rounded portion is sufficiently large that the separation between the closest extent of the external termination side extension and the inner conductive electrode is larger than the separation between the secondary portion and the external termination of opposing polarity.
The dielectric ceramic layers preferably comprise a dielectric ceramic composition. The major constituent material for the ceramic, for example, may be made of BaTiO3, BaCaTiZrO3, BaCaZrO3, BaZrO3, CaZrO3 and/or CaTiO3 but the current invention is not particularly limiting to the type of ceramic dielectric material used and other dielectric materials, insulators, magnetic materials and semiconductor materials, or combinations thereof, as known in the art. The dielectric ceramic composition can be used in conjunction with precious metal or base metal inner electrodes. Cheaper base metal electrodes are most preferred and they require a non-reducible ceramic which can be sintered in a reducing atmosphere below the melting temperature of common base metals, such as nickel, without detriment to the electrode thereby yielding a capacitor with high electrode continuity and excellent electrical properties.
The conductive inner electrodes comprise precious metal or base metal. Common base metals include nickel, tungsten, molybdenum, aluminum, chromium, copper or an alloy thereof which can be fired in a reducing atmosphere. Common precious metals are silver, palladium, platinum, gold or alloys thereof. Most preferably the base metal is nickel.
The composition of the external terminations and side extensions is not particularly limiting herein and any composition typically employed in the art is sufficient. Silver, palladium, copper, nickel or alloys of these metals compatible with the inner electrodes blended with various glass frits are particularly relevant. A plating layer or multiple plating layers can be formed on the external end terminations.
Because of the use of base metals in the conductive inner electrodes, the capacitor of the present invention is preferably fired in a reducing atmosphere. The reducing overall atmosphere average PO2 is preferably between 10−3 to 10−18 atm, while the PO2 in localized regions within the capacitor monolith have been estimated to be as low as ˜10−28 atm (C. A. Randall, et al., “A Structure-Property-Processing Approach Targeted to the Challenges in Capacitive Ceramic Devices,” CARTS USA 2006 P
An advantage of the present invention is the ability to use the same materials commonly employed and the conventional tape casting process familiar to those skilled in the art. In this process the ceramic powder, such as the preferred base metal compatible X7R dielectric comprising a substantial portion of barium titanate, is dispersed in an organic medium then cast into a tape.
Some of the tape is printed with the electrode pattern, in this case a paste of nickel in organic medium.
Merely as an example of the manufacturing process of the present invention, a ceramic slurry is prepared by blending and milling the ceramic compounds of choice with a dispersant in either water or an organic solvent such as, for example, ethanol, isopropanol, toluene, ethyl acetate, propyl acetate, butyl acetate or a blend thereof. After milling a ceramic slip is prepared for tape-casting by adding a binder and a plasticizer to control rheology.
The slip is then processed into a thin sheet by tape-casting. After drying the sheet, a multiplicity of electrodes are patterned on the sheet by using, for example, a screen-printing method to form a printed ceramic sheet.
A laminate green body is prepared by stacking onto a substance such as polycarbonate, polyester or a similar method: 1) a certain number of unprinted ceramic sheets representing the bottom covers, then 2) a certain number of printed ceramic sheets in alternate directions so as to create alternating electrodes that terminate at opposing ends, and 3) a certain number of unprinted ceramic sheets representing the top covers. Variations in the stacking order of the printed and unprinted sheets can be used with the dielectric material of this invention. The stack is then pressed at between 20° C. and 120° C. to promote adhesion of all laminated layers. The laminated green body is then cut into individual green chips.
Capacitors made with precious metal inner electrodes can be sintered in air up to temperatures not exceeding 1400° C. In the case of base metals the ceramic is then sintered in a reductive atmosphere with a partial oxygen partial pressure of 10−3 to 10−18 atm at a temperature not to exceed approximately 1500° C.
The sintered capacitor is preferably subjected to end surface grinding by barrel or sand blast, as known in the art, followed by applying external electrode paste to form the terminations to the inner electrode. A further firing is then done to complete the formation of the termination. For precious metal electrodes this firing is typically done in air at temperatures of about 500° C. to 900° C. For base metals this firing is typically done in nitrogen atmosphere at a temperature of about 600° C. to 1000° C. for about 0.1 to 1 hour.
Layers of nickel and tin may then be plated on the outer electrodes to enhance solderability and prevent oxidation of the outer electrodes.
A particularly preferred embodiment of the invention is illustrated in
The advantage of a symmetrical electrode, as described relative to
A capacitor formed utilizing the symmetrical electrode of
As would be realized from the discussion relative to
The following examples use tapes made of the same material and with the same fired thickness of 0.001″ (25.4 μm). All of the parts utilized a 1206 case size manufactured with the same materials by the same process the only factor affecting the electrical properties is the overlap area A which is a function of the design of the internal conductive electrode. No coatings were applied to these capacitors. Conductor designs are described in more detail in Table 1 and in the examples.
A basic MLCC was manufactured using the active overlap pattern shown in
A similar active design was used to the design described in Example 1 above accept that additional first and last prints were added with a top and bottom shield electrode pattern with the intermediate actives identical to those described in Example 1. This top and bottom shield electrode pattern is shown in
In addition to using the top and bottom shields described in Example 2 the side shields were used in the intermediate actives as shown in
Top and bottom shields as described in Examples 2 and 3 were used but there are no side shields in the active layers as described
A semi-circle tapered design was used at the end of the electrode. In this case the maximum extent of the electrode (A4) is 2.02 mm (0.0795 inches), after firing, which is the same as examples 5 and 7. The intermediate active prints are shown in
The electrical properties of Examples 1-8 are summarized in Table 3.
This electrical data shows the average capacitance of an MLCC made with the design described in Examples 4, 5, 6, 7 and 8 are higher than in comparative Example 3. Example 4 has a capacitance of 85.34 nF compared to 81.01 nF for the patented design in Example 3. Example 4 has 5.3% more capacitance than Example 3. Table 3 shows the standard deviations (a) associated with these capacitance measurements. The 30 associated with Examples 3 and 4 are 2.22 nF and 1.65 nF, respectively, and since the increased capacitance of 4.33 nF is higher than the combination of these (3.87 nF) the results are significant. The minimum voltage breakdown for Examples 4, 5, 6, and 7 are higher, in all cases, than the minimum of 1120 V recorded for Example 3. The minimum voltage breakdown is a good indicator of the design capability so the new designs disclosed in Examples 4, 5, 6, 7 and 8 offers an increased capacitance over Example 3 with similar voltage capability. The present invention provides capacitors with a break down voltage of over 1120 volts.
It should also be noted that although Examples 1 and 2 have the highest capacitance their voltage breakdowns are lower than all the other examples. Furthermore, it can be seen that the highest minimum breakdown voltage was 1350 V for Example 7, the highest capacitance obtained for the inventive design that is 34.6% higher capacitance than Example 3. The semi-circle electrode pattern described in Example 8 has a similar capacitance to Example 7 but the Average, Maximum and Minimum UVBD are all slightly less for Example 8.
Four batches of MLCC were manufactured with the electrode pattern of
As can be realized from the data presented in Table 4, a single electrode pattern provides a high capacitance with a high breakdown voltage which is otherwise unavailable. The capacitance values exceed those presented in Example 3 of U.S. Pat. No. 7,336,475 even allowing for the additional capacitance attributable to and additional 2 electrode prints which are used as shields. A single pattern would not be useable in the teachings of U.S. Pat. No. 7,336,475 due to the formation of gaps in the top and bottom shields.
High voltage capacitor designs are demonstrated herein that provide higher capacitance and increased voltage handling capability than currently available in the prior art.
The invention has been described with particular reference to preferred embodiments without limitation thereto. One of skill in the art will realize additional alterations, embodiments and examples which are not specifically set forth but which are within the meets and bounds of the invention as more specifically set forth in the claims appended hereto.
The present application is a divisional application of pending U.S. patent application Ser. No. 12/828,434 filed Jul. 2, 2010, which claims priority to expired U.S. Provisional Application No. 61/222,296 filed Jun. 1, 2009.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4097911 | Dorrian | Jun 1978 | A |
| 4241378 | Dorrian | Dec 1980 | A |
| 5144527 | Amano et al. | Sep 1992 | A |
| 5295289 | Inagaki | Mar 1994 | A |
| 5493769 | Sakai | Feb 1996 | A |
| 5692280 | Taniguchi | Dec 1997 | A |
| 6104599 | Ahiko et al. | Aug 2000 | A |
| 6134098 | Kuroda et al. | Oct 2000 | A |
| 6292353 | Haratani et al. | Sep 2001 | B1 |
| 6292535 | Williams et al. | Sep 2001 | B1 |
| 6563689 | Yamamoto | May 2003 | B2 |
| 6627529 | Ireland | Sep 2003 | B2 |
| 6683782 | Duva | Jan 2004 | B2 |
| 6829134 | Yamauchi et al. | Dec 2004 | B2 |
| 6898069 | Yamaguchi et al. | May 2005 | B2 |
| 7027288 | Shimizu et al. | Apr 2006 | B2 |
| 7336475 | Bultitude et al. | Feb 2008 | B2 |
| 7495885 | Togashi et al. | Feb 2009 | B2 |
| 7715171 | Nakano et al. | May 2010 | B2 |
| 7859821 | Shimizu | Dec 2010 | B2 |
| 8102639 | Kasuya | Jan 2012 | B2 |
| 8120891 | Takashima et al. | Feb 2012 | B2 |
| 8885319 | Bultitude | Nov 2014 | B2 |
| 20060213603 | Lee et al. | Sep 2006 | A1 |
| 20060215349 | Lee et al. | Sep 2006 | A1 |
| 20080165468 | Berolini et al. | Jul 2008 | A1 |
| 20090052111 | Bultitude et al. | Feb 2009 | A1 |
| 20090052122 | Johnson et al. | Feb 2009 | A1 |
| 20100039749 | Ritter et al. | Feb 2010 | A1 |
| 20100091429 | Koga et al. | Apr 2010 | A1 |
| Number | Date | Country |
|---|---|---|
| 0866478 | Jun 2005 | EP |
| 05135990 | Jun 1993 | JP |
| 06069063 | Mar 1994 | JP |
| 8181033 | Jul 1996 | JP |
| 09190946 | Jul 1997 | JP |
| 09270360 | Oct 1997 | JP |
| 2000106321 | Apr 2000 | JP |
| 2001015373 | Jan 2001 | JP |
| 2002299148 | Oct 2002 | JP |
| 2005216955 | Aug 2005 | JP |
| 20060666831 | Mar 2006 | JP |
| 2006128283 | May 2006 | JP |
| 2006190774 | Jul 2006 | JP |
| 2007299984 | Nov 2007 | JP |
| WO 2009001842 | Dec 2009 | WO |
| Entry |
|---|
| European Patent Application No. 10794758.2; Supplementary European Search Report dated Jan. 2, 2013. |
| International Search Report and Written Opinion of the International Searching Authority; PCT/US2010/040754, Sang Min Lee; Feb. 25, 2011. |
| Number | Date | Country | |
|---|---|---|---|
| 20140230210 A1 | Aug 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12828434 | Jul 2010 | US |
| Child | 14266364 | US |
