Method of manufacturing a semiconductor device

Abstract

Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view illustrating the layout constitution of elements formed over a chip in Embodiment 1 of the present invention;

FIG. 2 is a block diagram illustrating one example of the internal constitution of the EEPROM illustrated in FIG. 1;

FIG. 3 is a cross-sectional view illustrating the cross-section of a semiconductor device of Embodiment 1;

FIG. 4 is a schematic view illustrating one example of the memory array structure and operation conditions (1 cell/1 transistor) of the EEPROM illustrated in FIG. 1;

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to Embodiment 1;

FIG. 6 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 5;

FIG. 7 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 6;

FIG. 8 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 7;

FIG. 9 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 8;

FIG. 10 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 9;

FIG. 11 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 10;

FIG. 12 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 11;

FIG. 13 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 12;

FIG. 14 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 13;

FIG. 15 is a cross-sectional view illustrating a manufacturing step of the semiconductor device in a modification example;

FIG. 16 is a cross-sectional view illustrating a manufacturing step of the semiconductor device in another modification example;

FIG. 17 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 14;

FIG. 18 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 17;

FIG. 19 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 2;

FIG. 20 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 3;

FIG. 21 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 20;

FIG. 22 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 21;

FIG. 23 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 22;

FIG. 24 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 23;

FIG. 25 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 4;

FIG. 26 is a cross-sectional view illustrating the cross-section of a semiconductor device according to Embodiment 5;

FIG. 27 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to Embodiment 5;

FIG. 28 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 27;

FIG. 29 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 28;

FIG. 30 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 29;

FIG. 31 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 30;

FIG. 32 is a cross-sectional view illustrating the cross-section of a semiconductor device according to Embodiment 6;

FIG. 33 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to Embodiment 6;

FIG. 34 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 33;

FIG. 35 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 34;

FIG. 36 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 35;

FIG. 37 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 36;

FIG. 38 is a cross-sectional view illustrating a manufacturing step of a semiconductor device investigated by the present inventor;

FIG. 39 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 38;

FIG. 40 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 39;

FIG. 41 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 40;

FIG. 42 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 41;

FIG. 43 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 42;

FIG. 44 is a cross-sectional view illustrating a manufacturing step of another semiconductor device investigated by the present inventor;

FIG. 45 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 44;

FIG. 46 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 45;

FIG. 47 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 46;

FIG. 48 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 47; and

FIG. 49 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following the step of FIG. 48.

Claims

1. A manufacturing method of a semiconductor device for forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of the semiconductor substrate, which comprises the steps of: (a) forming a first insulating film over the semiconductor substrate including the first region and the second region;(b) forming a first conductor film over the first insulating film;(c) removing the first conductor film and the first insulating film formed over the second region;(d) after the step (c), forming a second insulating film over the semiconductor substrate including the second region and the first conductor film including the first region;(e) forming a second conductor film over the second insulating film;(f) patterning the second conductor film and the second insulating film to form a second gate electrode of the second MISFET in the second region; and(g) after the step (f), patterning the first conductor film and the first insulating film formed in the first region to form a first gate electrode of the first MISFET in the first region.

2. A manufacturing method of a semiconductor device according to claim 1, wherein the first region is a memory cell formation region, while the second region is a region other than the memory cell formation region.

3. A manufacturing method of a semiconductor device according to claim 1, wherein the first region is a region other than a memory cell formation region and the second region is the memory cell formation region.

4. A manufacturing method of a semiconductor device according to claim 1, wherein the first MISFET is an n channel MISFET, while the second MISFET is a p channel MISFET.

5. A manufacturing method of a semiconductor device according to claim 1, wherein in the step (f), the second conductor film and the second insulating film are patterned to form a second gate electrode of the second MISFET in the second region and remove the second conductor film and the second insulating film from the first region.

6. A manufacturing method of a semiconductor device according to claim 1, wherein in the step (f), the second conductor film and the second insulating film are patterned to form a second gate electrode of the second MISFET in the second region, and of the second conductor film and the second insulating film formed in the first region, remove the second conductor film and the second insulating film formed in a region other than the second electrode formation region of the first region while leaving the second conductor film and the second insulating film formed over the first gate electrode formation region of the first MISFET, andwherein in the step (g), the first conductor film and the first insulating film are patterned with the second conductor film and the second insulating film formed over the first gate electrode formation region as a hard mask, whereby a first gate electrode of the first MISFET is formed in the first region.

7. A manufacturing method of a semiconductor device according to claim 1, wherein a dummy pattern has been formed in the boundary region between the first region and the second region.

8. A manufacturing method of a semiconductor device according to claim 1, wherein the first MISFET is a transistor constituting a nonvolatile memory cell.

9. A manufacturing method of a semiconductor device according to claim 8, wherein the first insulating film is a film stack of a first potential barrier film, a charge storage film and a second potential barrier film.

10. A manufacturing method of a semiconductor device according to claim 9, wherein the first potential barrier film and the second potential barrier film have been made of a silicon oxide film and the charge storage film has been made of a silicon nitride film.

11. A manufacturing method of a semiconductor device according to claim 1, wherein the second MISFET is a transistor constituting a nonvolatile memory cell.

12. A manufacturing method of a semiconductor device according to claim 11, wherein the second insulating film is a film stack of a first potential barrier film, a charge storage film and a second potential barrier film.

13. A manufacturing method of a semiconductor device according to claim 12, wherein the first potential barrier film and the second potential barrier film have been made of a silicon oxide film, and the charge storage film has been made of a silicon nitride film.

14. A manufacturing method of a semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are different in film thickness.

15. A manufacturing method of a semiconductor device according to claim 14, wherein the second insulating film has a smaller film thickness than the first insulating film.

16. A manufacturing method of a semiconductor device according to claim 15, wherein the first conductor film has been made of a polysilicon film and the second conductor film has been made of a metal film.

17. A manufacturing method of a semiconductor device according to claim 1, wherein the first conductor film and the second conductor film have been made of a metal film, the first MISFET is an n channel MISFET, and the second MISFET is a p channel MISFET.

18. A manufacturing method of a semiconductor device according to claim 1, wherein the first conductor film and the second conductor film have been made of a metal film, the first MISFET is a p channel MISFET, and the second MISFET is an n channel MISFET.

19. A manufacturing method of a semiconductor device according to claim 17, wherein the first insulating film and the second insulating film are each a high dielectric constant film having a higher dielectric constant than a silicon oxide film.

20. A manufacturing method of a semiconductor device according to claim 1, further comprising a step of forming a capacitor element having the first conductor film as a lower electrode and the second conductor film as an upper electrode in a third region of the semiconductor substrate.

21. A manufacturing method of a semiconductor device according to claim 18, wherein the first insulating film and the second insulating film are each a high dielectric constant film having a higher dielectric constant than a silicon oxide film.