Claims
- 1. A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first insulating layer in a selected region on a semiconductor layer;
- forming a second insulating layer on a surface and a side wall of said first insulating layer;
- etching back said second insulating layer to leave a first side wall insulating layer on the side wall of said first insulating layer;
- mesa-etching said semiconductor layer by anisotropic dry etching, using said first insulating layer and said first side wall insulating layer as masks, to form a side wall for element isolation;
- forming a source electrode and a drain electrode in a selected region of the surface of said semiconductor layer;
- forming a third insulating layer having a gate opening on the surface of said semiconductor layer;
- forming a fourth insulating layer on a surface and an end face of said gate opening;
- etching back said fourth insulating layer to leave a second side wall insulating layer on a side wall of said gate opening of said third insulating layer;
- gate-recess-etching said semiconductor layer by said anisotropic dry etching, using said third insulating layer and said second side wall insulating layer as masks, to form a gate recess thereon;
- forming a fifth insulating layer on the entire surface of a resultant structure and etching back said fifth insulating layer to form a third side wall insulating layer on a side wall of said gate recess; and
- forming a gate electrode in said gate recess.
- 2. The method according to claim 1, wherein said first side wall insulating layer and said second side wall insulating layer are formed in the shape of a forward taper, and said shape is transferred onto said side wall for element isolation and said side wall of said gate recess by said anisotropic etching.
- 3. The method according to claim 1, wherein said gate electrode is formed so as to have a T-shaped cross section, and said third side wall insulating layer is formed around a leg portion of said gate electrode.
Priority Claims (1)
Number |
Date |
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1-334548 |
Dec 1989 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/631,840, filed Dec. 21, 1990, now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (10)
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JPX |
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0028923 |
Jan 1989 |
JPX |
2020021 |
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JPX |
Non-Patent Literature Citations (3)
Entry |
Simple method to create tapering trenches; IBM Tech. Dis. Bulletin, vol. 27, No. 10B; Mar. 1985; 5996-5997. |
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 4883-4885; "Method For Controlling via Sidewall Slope", Chang et al. |
Wolf et al. "Silicon Processing for the VLSI Era"; vol. 1, 1986, pp. 539-542. |
Continuations (1)
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Number |
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631840 |
Dec 1990 |
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