Claims
- 1. A method of manufacturing a semiconductor integrated circuit device having bit lines, word lines and memory cells each including a MISFET and a capacitor element, each memory cell being connected to one of said word lines and said bit lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region for said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing a polishing of the surface of said first insulating film; (d) forming a second insulating film over said first insulating film; (e) forming grooves in said second insulating film; (f) forming a first conductive film in said grooves, for forming said bit lines; (g) forming a third insulating film over said second insulating film; (h) forming openings in said second insulating film and said third insulating film; (i) forming second conductive films over said openings, wherein one of said second conductive films is connected to one of said source and drain regions of said MISFET; (j) forming a dielectric film on said second conductive films; and (k) forming a third conductive film over said dielectric film.
- 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps, between steps (c) and (d), of:(l) performing an etching of said first insulating film in order to form a through hole exposing the other of said source and drain regions of said MISFET; and (m) forming a second conductor strip in said through hole, wherein said second conductor strip is connected to one of said bit lines.
- 3. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein step (f) comprises the substeps of:(n) depositing a conductive layer on said second insulating film; and (o) polishing said conductive layer, for forming said bit lines in said grooves, wherein portions of said conductive layer outside said grooves are removed.
- 4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step, between steps (c) and (d), of:(p) depositing a fourth insulating film on said first insulating film, wherein said second insulating film is etched faster than said fourth insulating film, as a result of a difference of etching rate between said first insulating film and said fourth insulating film.
- 5. A method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said first insulating film and said fourth insulating film are comprised of silicon oxide and silicon nitride, respectively.
- 6. A method of manufacturing a semiconductor integrated circuit device having bit lines, word lines and memory cells each including a MISFET and a capacitor element, each memory cell being connected to one of said word lines and said bit lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region for said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing a polishing of the surface of said first insulating film; (d) forming a second insulating film over said first insulating film; (e) forming grooves in said second insulating film; (f) forming a conductive film in said grooves, for forming said bit lines; and (g) forming capacitors over said bit lines, wherein said capacitors are connected to one of said source and drain regions of said MISFET.
Priority Claims (2)
Number |
Date |
Country |
Kind |
8-302821 |
Nov 1996 |
JP |
|
9-283419 |
Oct 1997 |
JP |
|
Parent Case Info
This application is a Continuation application of application Ser. No. 09/332,894, filed Jun. 15, 1999, now U.S. Pat. No. 6,168,985 which is a Continuation application of application Ser. No. 08/968,586, filed Nov. 13, 1997 now U.S. Pat. No. 6,037,207.
US Referenced Citations (7)
Number |
Name |
Date |
Kind |
5288655 |
Higasitani et al. |
Feb 1994 |
A |
5320976 |
Chin et al. |
Jun 1994 |
A |
5364811 |
Ajika et al. |
Nov 1994 |
A |
5378532 |
Hamamoto et al. |
Jan 1995 |
A |
5387532 |
Hamamoto et al. |
Feb 1995 |
A |
5438008 |
Ema |
Aug 1995 |
A |
5604365 |
Kajigaya et al. |
Feb 1997 |
A |
Foreign Referenced Citations (1)
Number |
Date |
Country |
7-122654 |
May 1995 |
JP |
Non-Patent Literature Citations (1)
Entry |
Kang, et al., “Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMS”, IEDM-1994. |
Continuations (2)
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Number |
Date |
Country |
Parent |
09/332894 |
Jun 1999 |
US |
Child |
09/642586 |
|
US |
Parent |
08/968586 |
Nov 1997 |
US |
Child |
09/332894 |
|
US |