Method of manufacturing interconnect substrate

Abstract

A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method including: (a) forming a plurality of rows of linear catalyst layers on a substrate; and (b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers, at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a diagram showing a method of manufacturing an interconnect substrate according to a first embodiment of the invention.

FIG. 2 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 3 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 4 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 5 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 6 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 7 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 8 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 9 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 10 is a diagram showing the method of manufacturing an interconnect substrate according to the first embodiment.

FIG. 11 is a graph showing measurement results according to a first experimental example of the invention.

FIG. 12 shows an example of an electronic device to which an interconnect substrate according to one embodiment of the invention is applied.

FIG. 13 is a diagram showing a method of manufacturing an interconnect substrate according to a modification of the first embodiment.

FIG. 14 is a diagram showing a method of manufacturing an interconnect substrate according to a second embodiment of the invention.

FIG. 15 is a graph showing measurement results according to a third experimental example of the invention.

FIG. 16 is a diagram showing a method of manufacturing an interconnect substrate according to a modification of the second embodiment.

Claims

1. A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method comprising: (a) forming a plurality of rows of linear catalyst layers on a substrate; and(b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers,at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.

2. The method of manufacturing an interconnect substrate as defined in claim 1, wherein the total line width of the linear catalyst layers on the substrate is 20 micrometers or more.

3. The method of manufacturing an interconnect substrate as defined in claim 1, wherein the rows of metal layers include interconnects and dummy interconnects.

4. The method of manufacturing an interconnect substrate as defined in claim 3, wherein the dummy interconnects are formed on both sides of the interconnect.

5. The method of manufacturing an interconnect substrate as defined in claim 1, further comprising: forming a resist layer on the substrate in a region other than a region of a desired interconnect pattern before the step (a); andforming a surfactant layer on the substrate before the step (a),wherein the step (a) includes:forming a linear catalyst layer on the surfactant layer; andremoving the resist layer to remove part of the surfactant layer and the catalyst layer in the region other than the region of the desired interconnect pattern.

6. The method of manufacturing an interconnect substrate as defined in claim 1, wherein, in the step (b), nickel is deposited on the linear catalyst layers by immersing the substrate in an electroless plating solution including nickel.

7. A method of manufacturing an interconnect substrate by electroless plating without using a plating resist, the method comprising: (a) forming catalyst layers in a plurality of regions on a substrate; and(b) depositing a metal on the catalyst layers by electroless plating to form metal layers in the regions,part of the catalyst layers formed in at least one of the regions having an area of 4 square micrometers or less, and a total area of the catalyst layers being 49 square micrometers or more.

8. The method of manufacturing an interconnect substrate as defined in claim 7, wherein another catalyst layer for forming a dummy interconnect is formed around the part of the catalyst layers formed in the one region.

9. The method of manufacturing an interconnect substrate as defined in claim 7, further comprising: forming a resist layer on the substrate in a region other than a region of a desired interconnect pattern before the step (a); andforming a surfactant layer on the substrate before the step (a),wherein the step (a) includes:forming a catalyst layer on the surfactant layer; andremoving the resist layer to remove part of the surfactant layer and the catalyst layer in the region other than the region of the desired interconnect pattern.

10. The method of manufacturing an interconnect substrate as defined in claim 7, wherein, in the step (b), nickel is deposited on the catalyst layers by immersing the substrate in an electroless plating solution including nickel.