The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing salicide layers of a semiconductor device.
As the size of the semiconductor device is gradually shortened, it is important to reduce the resistance of the semiconductor device and reduce the junction leakage current in order to increase the response speed (e.g. switching frequency) and reduce power consumption. For achieving the above purposes, a method of forming two salicide layers with different materials or different thicknesses is disclosed. These two salicide layers are located at two different regions of the semiconductor device. For example, two self-aligned salicide layers (also referred as salicide layers) with different thicknesses are respectively formed in the gate region and the source/drain region of a MOS transistor in order to achieve the above purposes. However, the process of forming two salicide layers at two different regions is complicated.
Therefore, there is a need of providing an improved method of manufacturing salicide layers in order to obviate the drawbacks encountered from the prior art.
In accordance with an aspect, the present invention provides a method of manufacturing salicide layers in the fabrication of a semiconductor device. The method includes the following steps. Firstly, a silicon substrate with a patterned stack structure of a silicon layer and a first cap layer sequentially formed thereon is provided. Then, a second cap layer is formed on the exposed silicon substrate. The materials of the first cap layer and the second cap layer are different. Then, the first cap layer is removed to expose the silicon layer. Then, a first metal layer is formed on the silicon layer and reacted with the silicon layer to produce a first salicide layer. Afterward, the second cap layer is removed, and a second metal layer is formed over the surface of the silicon substrate and reacted with the silicon substrate to produce a second salicide layer.
In an embodiment, before forming the patterned stack structure, a first dielectric layer is formed over the surface of the silicon substrate.
In an embodiment, before removing the first cap layer, a second dielectric layer is formed over the first cap layer and the patterned stack structure, and a part of the second dielectric layer and a part of the first dielectric layer are then etched back to form a spacer beside the pattern stack structure and a portion of the surface of the silicon substrate is exposed.
In an embodiment, the first dielectric layer is formed by a thermal oxidation process or a chemical vapor deposition process.
In an embodiment, the second dielectric layer is formed of silicon dioxide.
In an embodiment, the first cap layer is formed of silicon nitride.
In an embodiment, before removing the second cap layer, a doped region can be formed in the silicon substrate beside the patterned stack structure. Then, a high-temperature annealing process may be performed to treat the doped region.
In an embodiment, before removing the second cap layer, a doped region is formed in the silicon substrate beside the patterned stack structure and then a high-temperature annealing process to treat the doped region is performed.
In an embodiment, an oxygen gas is further fed in the high-temperature annealing process to form the second cap layer by a thermal oxidation process.
In an embodiment, the method of forming the first salicide layer includes forming a first metal layer on the silicon layer and reacted with each other to form the first salicide layer.
In an embodiment, an annealing process is performed twice after forming the first metal layer.
In an embodiment, the method of forming the second salicide layer includes forming a second metal layer on the silicon substrate and reacted with each other to form the second salicide layer.
In an embodiment, an annealing process is performed twice after forming the second metal layer.
In an embodiment, a thickness of the second salicide metal layer is different from that of the first metal salicide layer.
In an embodiment, a thickness of the second salicide metal layer is smaller than that of the first salicide metal layer.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
Firstly, as shown in
In other embodiments, the first dielectric layer 21 exposed by the stack structure 311 also can be removed to expose a portion of the surface 11 of the substrate 10 beside the stack structure 311.
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
As known, in the conventional method of fabricating a MOSFT device, the polysilicon layer at the top surface of gate electrode is at the same level as the top surface of the spacer. Whereas, according to the present invention, after the selective etching process is performed, the surface of the silicon layer 31a is slightly lower than the spacer 321 by a height difference d4 (see
After the step of
It is noted that the first metal layer 42 and the second metal layer 23 may be made of different materials. Further, the first metal layer 42 should be capable of bearing higher temperature than the second metal layer 23 to prevent the first metal layer 42 from being damaged during the process of forming the second metal layer 23. Moreover, for increasing the response speed of the semiconductor device and reducing the junction leakage current, it is preferred that the thickness of the second metal layer 23 is smaller than the thickness of the first metal layer 42. Consequently, after the reaction is carried out, the thickness d2 of the second salicide layer 231 is, for example, smaller than the thickness dl of the first salicide layer 421.
From the above description, the method of the present invention is capable of forming two salicide layers with different materials or different thicknesses at two different region of a semiconductor device by using reduced number of photolithography and etching processes. Consequently, the purposes of increasing the response speed of the semiconductor device and reducing the junction leakage current are both achieved. That is, the fabricating cost is reduced, and the size of the semiconductor device is reduced.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.