This application claims priority to China Application Serial Number 202110833924.X, filed Jul. 23, 2021, which is herein incorporated by reference.
The present invention relates to a method of manufacturing a phase change memory and a phase change memory.
Electronic products (e.g., mobile phones, tablets, and digital cameras) often have memory elements that store data. Conventional memory elements can store information through storage nodes of memory units. Among them, the phase change memory uses resistance states (e.g., high resistance and low resistance) of the memory element to store information. The memory element may have a material that can be switched between different phase states (e.g., a crystalline phase and an amorphous phase). The different phase states enable the memory unit to have different resistance states for representing different values of stored data.
Generally, an accurate alignment is required when manufacturing a phase change memory, so that the process is complicated and difficult to be controlled, and the manufacturing cost of the phase change memory is increased. Moreover, a word line metal layer, a phase change material layer, a bit line metal layer and the like are directly formed on a wafer having, such as, CMOS, and the characteristic of the CMOS is degraded by a high temperature during the crystallization of the phase change material layer. Therefore, a novel and efficient process for manufacturing a phase change memory is urgently needed.
An object of the present invention is to provide a method of manufacturing a phase change memory and a phase change memory capable of solving one or more deficiencies of the related art.
In one embodiment, the present invention provides a method of manufacturing a phase change memory, comprising: forming a first wafer having a semiconductor-on-insulator structure; forming a memory material layer on the semiconductor-on-insulator structure; and forming a first metal material layer on the memory material layer to form a first semiconductor element.
In some embodiments, forming the first wafer comprises: forming an insulating layer on a substrate; forming a semiconductor layer on the insulating layer to form the semiconductor-on-insulator structure; and performing N-type and P-type doping on the semiconductor layer to form a selector.
In some embodiments, the method further comprises: forming a memory array in the first semiconductor element, the memory array comprising a plurality of memory units formed in the memory material layer, a plurality of selector units formed in the semiconductor-on-insulator structure, and a plurality of first metal regions formed in the first metal material layer.
In some embodiments, the method further comprises: forming a second semiconductor element, wherein the second semiconductor element comprises a second wafer having a first contact region and a second contact region; and flipping the first semiconductor element and bonding a first surface of the first semiconductor element with a first surface of the second semiconductor element.
In some embodiments, the method further comprises: removing the substrate to expose the insulating layer after bonding the first surface of the first semiconductor element with the first surface of the second semiconductor element.
In some embodiments, removing the substrate comprises: grinding, polishing and/or etching a second surface of the first semiconductor element to expose the insulating layer.
In some embodiments, bonding the first surface of the first semiconductor element with the first surface of the second semiconductor element comprises: aligning and connecting the first metal region of the first semiconductor element with the first contact region of the second semiconductor element.
In some embodiments, the method, after removing the substrate to expose the insulating layer, further comprises: forming a first contact hole in the insulating layer; and forming a second metal material layer in the insulating layer, wherein the second metal material layer is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the first contact hole.
In some embodiments, the method further comprises: before flipping the first semiconductor element, forming a first connection channel in the first semiconductor element comprising the memory array, wherein the first connection channel comprises a first connection region and a second connection region electrically isolated from each other, and the first connection region is connected to the first metal region through a first connection hole.
In some embodiments, bonding the first surface of the first semiconductor element with the first surface of the second semiconductor element further comprises: aligning and connecting the first connection region and the second connection region of the first semiconductor element with the first contact region and the second contact region of the second semiconductor element, respectively.
In some embodiments, the method, after removing the substrate to expose the insulating layer, further comprises: forming a second contact hole in the insulating layer; and forming a second metal material layer in the insulating layer, wherein the second metal material layer is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the second connection region and the second contact hole.
In some embodiments, the method, before flipping the first semiconductor element, further comprises: forming a second connection channel in the first semiconductor element comprising the memory array, wherein the second connection channel comprises a third connection region connected to the first metal region through a second connection hole; forming a first oxide layer having a first thickness on the third connection region of the first semiconductor element; and forming a second oxide layer having a second thickness on the first contact region and the second contact region of the second semiconductor element.
In some embodiments, the first oxide layer and the second oxide layer comprise same material.
In some embodiments, bonding the first surface of the first semiconductor element with the first surface of the second semiconductor element further comprises: aligning the first oxide layer of the first semiconductor element with the second oxide layer of the second semiconductor element.
In some embodiments, the method, after removing the substrate to expose the insulating layer, further comprises: forming a plurality of third contact holes in the insulating layer; and forming a second metal material layer in the insulating layer, wherein the second metal material layer comprises a plurality of second metal regions having a first portion and a second portion electrically isolated from each other, wherein the first portion of the plurality of second metal regions is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the third contact hole, and wherein the second portion of the plurality of second metal regions is connected to the third connection region of the second connection channel through the third contact hole, and connected to the first contact region of the second semiconductor element through the third contact hole.
In some embodiments, the memory material layer is a phase change memory material layer.
In some embodiments, the memory material layer is a non-volatile memory material layer comprising one or more of a voltage controlled resistor, a memory resistor and a resistor random access memory.
The present invention also provides a phase change memory, comprising: a first semiconductor element comprising a first wafer having a semiconductor-on-insulator structure, a selector formed on the semiconductor-on-insulator structure, a memory material layer formed on the selector, and a first metal material layer formed on the memory material layer.
In some embodiments, the first semiconductor element further comprises a memory array, the memory array comprising: a plurality of memory units formed in the memory material layer; a plurality of selector units formed in the semiconductor-on-insulator structure; and a plurality of first metal regions formed in the first metal material layer.
In some embodiments, the first wafer comprises: an insulating layer formed on a removable substrate, wherein the selector is formed by forming a semiconductor layer on the insulating layer to form the semiconductor-on-insulator structure, and performing N-type and P-type doping on the semiconductor layer.
In some embodiments, phase change memory further comprises: a second semiconductor element comprising a second wafer having a first contact region and a second contact region, wherein the first semiconductor element is flipped and mounted on the second semiconductor element, and a first surface of the first semiconductor element is bonded with a first surface of the second semiconductor element.
In some embodiments, the first metal region of the first semiconductor element is aligned and connected with the first contact region of the second semiconductor element.
In some embodiments, the first semiconductor element further comprises: a first contact hole formed in the insulating layer; and a second metal material layer formed in the insulating layer, wherein the second metal material layer is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the first contact hole.
In some embodiments, the first semiconductor element further comprises: a first connection channel having a first connection region and a second connection region electrically isolated from each other, wherein the first connection region is connected to the first metal region through a first connection hole, and wherein the first connection region and the second connection region of the first semiconductor element are aligned and connected with the first contact region and the second contact region of the second semiconductor element, respectively.
In some embodiments, the first semiconductor element further comprises: a second contact hole formed in the insulating layer; and a second metal material layer formed in the insulating layer, wherein the second metal material layer is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the second connection region and the second contact hole.
In some embodiments, the first semiconductor element further comprises: a second connection channel having a third connection region connected to the first metal region through a second connection hole; and a first oxide layer formed on the third connection region of the first semiconductor element, wherein the first oxide layer of the first semiconductor element is aligned and bonded with a second oxide layer formed on the first contact region and the second contact region of the second semiconductor element.
In some embodiments, the first oxide layer and the second oxide layer comprise same material.
In some embodiments, the first semiconductor element further comprises: a plurality of third contact holes formed in the insulating layer; and a second metal material layer formed in the insulating layer, the second metal material layer comprising a plurality of second metal regions having a first portion and a second portion electrically isolated from each other, wherein the first portion of the plurality of second metal regions is connected to the plurality of selector units, and connected to the second contact region of the second semiconductor element through the third contact hole, and wherein the second portion of the plurality of second metal regions is connected to the third connection region of the second connection channel through the third contact hole, and connected to the first contact region of the second semiconductor element through the third contact hole.
In some embodiments, the memory material layer is a phase change memory material layer.
In some embodiments, the memory material layer is a non-volatile memory material layer comprising one or more of a voltage controlled resistor, a memory resistor and a resistor random access memory.
In some embodiments, the first metal material layer is a metal material layer for forming a bit line, and the second metal material layer is a metal material layer for forming a word line.
According to the present invention, two wafers may be easily aligned and bonded with each other by forming P—N diodes as the selectors using the semiconductor-on-insulator structure, and transferring the layer between the wafers through oxide-oxide melted bonding or oxide-metal mixed bonding, thereby lowering the defect density and leakage without additional risks.
It should be understood that the above general description and the following detailed description are exemplary and are intended to provide a further explanation of the claimed invention.
The present invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings:
In order that the present invention is described in detail and completeness, implementation aspects and specific embodiments of the present invention with illustrative description are presented, but it is not the only form for implementation or use of the specific embodiments of the present invention. The embodiments disclosed herein may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description. In the following description, numerous specific details will be described in detail in order to enable the reader to fully understand the following embodiments. However, the embodiments of the present invention may be practiced without these specific details.
Further, spatially relative terms, such as “beneath,” “over,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as shown in the figures. The true meaning of the spatially relative terms includes other orientations. For example, when the figure is flipped up and down by 180 degrees, the relationship between one component and another component may change from “beneath” to “over.” The spatially relative descriptions used herein should be interpreted the same.
In some embodiments, the first semiconductor element 10 may further comprise a memory array MA. The memory array MA, for example, may comprise a plurality of memory units 141 formed in the memory material layer 14, a plurality of selector units 131A formed in the SOI structure, and a plurality of first metal regions 151 formed in the first metal material layer 15.
In some embodiments, the phase change memory 100 may further comprise a second semiconductor element 20. The second semiconductor element 20 may comprise a second wafer 21 having a first contact region 211 and a second contact region 212. The first semiconductor element 10 is flipped and mounted on the second semiconductor element 20, such that a first surface 101 of the first semiconductor element 10 is bonded with a first surface 201 of the second semiconductor element 20.
In some embodiments, as shown in
In another embodiment of the present invention, the first semiconductor element 10 may further comprise a contact hole 16 and a second metal material layer 17. The contact hole 16 is formed in the insulating layer 12. The second metal material layer 17 is formed in the insulating layer 12. The second metal material layer 17 is connected to the plurality of selector units 131A, and connected to the second contact region 212 of the second semiconductor element 20 through the contact hole 16.
Hereinafter, the method for manufacturing a phase change memory and a phase change memory manufactured by the method will be explained in details with reference to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
After the bonding process of step S206, as shown in
After removing the substrate 11 to expose the insulating layer 12, as shown in
As shown in
In some embodiments, the first semiconductor element 10C and the second semiconductor element 20A may be manufactured by same manufacturer, or may be manufactured by different manufacturers. After the first semiconductor element 10C and second semiconductor element 20A are manufactured separately in different processes, the layer may be transferred between the first and second semiconductor elements through bonding, thereby effectively preventing the characteristic of semiconductor component such as CMOS in the second semiconductor element 20A from being degraded by a high temperature during the crystallization of a phase change material layer in the first semiconductor element 10C.
In some embodiments, before flipping the first semiconductor element, the method 200 may further comprise, as shown in
In the step S206 of the method 200, as shown in
After the step S206, as shown in
Referring to
According to the present invention, the alignment and bonding may be more easily performed using the structure shown in
In some embodiments, before the step S206 in which the first semiconductor element is flipped, the method 200 may further comprises: as shown in
In the step S206 of the method 200, as shown in
After the step S206, as shown in
Referring to
In some embodiments, the first oxide layer 19 and the second oxide layer 22 may comprise the same material. According to the present invention, the alignment and bonding between the first semiconductor element 10E and the second semiconductor element 20B may be more easily performed using the structure shown in
As shown in
According to the present invention, the first semiconductor element comprising the first wafer and the second semiconductor element comprising the second wafer are manufactured separately, and then aligning and bonding with each other, such that an accurate alignment between the first semiconductor element and the second semiconductor element is not required, thereby simplifying the manufacturing process, lowering the manufacturing cost, and improving the manufacturing yield. Moreover, it is possible to effectively prevent the characteristic of the semiconductor component (e.g., CMOS) in the second semiconductor element from being degraded by a high temperature during the crystallization of the phase change material layer in the first semiconductor element.
Further, according to the present invention, two wafers may be easily aligned and bonded with each other by forming the P—N diode as the selector using the semiconductor-on-insulator structure, and transferring the layer between the wafers through oxide-oxide melted bonding or oxide-metal mixed bonding, thereby lowering the defect density and leakage without additional risks.
According to the present invention, an alignment area of the contact region is increased by providing the connection channel in the first semiconductor element, such that the alignment and bonding between the two elements may be easily performed.
According to the present invention, the alignment and bonding between the two elements may be easily performed by providing the oxide layer in each of the first semiconductor element and the second semiconductor element.
Although embodiments of the present invention have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the claim scope of the present invention should not be limited to the description of the embodiments contained herein.
It is obvious to those skilled in the art that various modifications and changes can be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover the modifications and changes of the present invention as long as they fall within the claim scope of the present invention.
Number | Date | Country | Kind |
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202110833924.X | Jul 2021 | CN | national |