This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-175443, filed on Sep. 19, 2018, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method of manufacturing a semiconductor device.
There is a technique of bonding two semiconductor substrates with a bonding layer containing a metal interposed therebetween. It is desired to prevent metal contamination originated from a bonding layer containing a metal when processing the bonded semiconductor substrates.
In this specification, the same or similar members are denoted by the same reference numerals, and in some cases, redundant description thereof may be omitted.
In this specification, in order to indicate the positional relationship of parts or the like, in some cases, the upward direction of the drawing may be described as “upper”, and the downward direction of the drawing may be described as “lower”. In this specification, the concepts of “upper” and “lower” are not necessarily terms indicating the relationship with the direction of gravity.
A method of manufacturing a semiconductor device according to an embodiment includes: forming a bonding layer containing a metal on a first surface of a first semiconductor substrate having the first surface and a first back surface; bonding the first semiconductor substrate and a second semiconductor substrate having a second surface and a second back surface so that the second surface is in contact with the bonding layer; and forming a coating layer covering the bonding layer on an outer peripheral portion of the second semiconductor substrate.
In the method of manufacturing a semiconductor device according to the embodiment, two semiconductor substrates are bonded to each other with a bonding layer containing a metal interposed therebetween, and the bonded semiconductor substrates are processed.
First, a first silicon wafer 11 (first semiconductor substrate) and a second silicon wafer 12 (second semiconductor substrate) are prepared.
The first silicon wafer 11 has a first surface 11a and a first back surface 11b. For example, a semiconductor element (not illustrated) is formed on the side of the first surface 11a of the first silicon wafer 11.
The second silicon wafer 12 has a second surface 12a and a second back surface 12b. For example, a semiconductor element (not illustrated) is formed on the side of the second surface 12a of the second silicon wafer 12.
Next, a bonding layer 14 containing a metal is formed on the first surface 11a of the first silicon wafer 11. The bonding layer 14 is not formed on the outer peripheral portion of the first silicon wafer 11.
The bonding layer 14 is, for example, a eutectic alloy.
Next, the first silicon wafer 11 and the second silicon wafer 12 are bonded so that the second surface 12a of the second silicon wafer 12 is in contact with the bonding layer 14 (
Next, a solder resist (coating material) for covering the side surface of the bonding layer 14 is applied to the region including the outer peripheral portion of the second silicon wafer 12. The solder resist is dropped from a nozzle onto the outer peripheral portion of the second silicon wafer 12 by using a known coating apparatus. By doing so, a solder resist layer 16 is formed (
The solder resist layer 16 is an example of a coating layer. The solder resist of the embodiment is a negative type photosensitive resin.
Next, a portion of the solder resist layer 16 on the second back surface 12b is exposed to light by using a known exposure apparatus, and a development process is performed. The solder resist layer 16 other than the exposed portion is removed by a development process. The solder resist layer 16 of the center portion is removed while the solder resist layer 16 of the outer peripheral portion of the second silicon wafer 12 remains (
In addition, herein, the outer peripheral portion of the second silicon wafer 12 includes at least the outer peripheral side surface of the second silicon wafer and the side surface of the bonding layer 14 in the vicinity of the outer peripheral side surface.
The solder resist layer 16 is in contact with the first surface 11a of the first silicon wafer 11 and the second back surface 12b of the second silicon wafer 12. The solder resist layer 16 prevents metal contamination originated from the bonding layer 14 from occurring in the subsequent manufacturing process. In addition, in the subsequent manufacturing process, it is prevented that the bonding layer 14 is unintentionally and greatly etched.
Next, the function and effect of the method of manufacturing a semiconductor device according to the embodiment will be described.
There is a technique of bonding two semiconductor substrates with a bonding layer containing a metal interposed therebetween. It is preferable to prevent metal contamination originated from the bonding layer containing a metal when processing a bonded semiconductor substrate.
In the method of manufacturing a semiconductor device according to the embodiment, a manufacturing process subsequent to the bonding of the first silicon wafer 11 and the second silicon wafer 12 with the bonding layer 14 containing a metal is, for example, a process of forming the wiring on the second back surface 12b of the second silicon wafer 12. Before the formation of the wiring, the solder resist layer 16 covering the bonding layer 14 is provided on the outer peripheral portions of the second silicon wafer 12 and the first silicon wafer 11. The formation of the wiring is performed in a state where the solder resist layer 16 to be the coating layer covers the bonding layer 14.
If the solder resist layer 16 does not cover the bonding layer 14, for example, after patterning the metal film to be the wiring, when the resist pattern is removed by wet etching, the bonding layer 14 is exposed to the wet etching solution. For this reason, metal contamination originated from the bonding layer 14 may occur. In addition, there is a concern that the bonding layer 14 may be unintentionally and greatly etched.
In addition, if the solder resist layer 16 does not cover the bonding layer 14, for example, when the underlying layer of the metal film to be the wiring is removed by wet etching, the bonding layer 14 is exposed to the wet etching solution. Therefore, there is a concern that metal contamination originated from the bonding layer 14 may occur. In addition, the bonding layer 14 may be unintentionally and greatly etched.
According to the method of manufacturing a semiconductor device of the embodiment, the solder resist layer 16 is provided, so that the bonding layer 14 is prevented from being exposed to the wet etching solution. Therefore, it is possible to realize the method of manufacturing a semiconductor device capable of preventing metal contamination originated from the bonding layer 14. As a result, it is possible to realize a semiconductor device having high yield and high reliability.
In the embodiment, the case where the coating layer contains a solder resist has been described as an example, but the coating layer is not limited to the solder resist, and, for example, other resins such as photosensitive polyimide or non-photosensitive polyimide may be used. In addition, the coating layer is not necessarily limited to a resin, but the coating layer may be an inorganic insulator such as an oxide film, a nitride film, or an oxynitride film.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the method of manufacturing a semiconductor device described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2018-175443 | Sep 2018 | JP | national |