Patent Application
20180204904
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-007429 filed on Jan. 19, 2017, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method of manufacturing a semiconductor device.
As a technique for optimizing a high-frequency signal processing or miniaturizing the entire semiconductor device, there is known a technique of forming a semiconductor device using a monolithic microwave integrated circuit (MMIC). In the MMIC, both an active element such as a field effect transistor (FET) and a passive element such as a capacitor are arranged on the same semiconductor substrate.
As a technique relating to the MMIC, Patent Document 1 discusses a method of manufacturing a semiconductor device within a short time by simultaneously forming the FET and the capacitor in the same step.
However, in the semiconductor device manufactured in this method, thicknesses of insulation films formed on the FET (active element) and the capacitor (passive element) become equal to each other. For this reason, the insulation film that covers a surface of the FET is thickened more than necessary depending on a specification of the capacitor (for example, a thickness of an interlayer insulation film), and this disadvantageously degrades a high-frequency characteristic of the FET.
A semiconductor device and a method of manufacturing the semiconductor device according to an embodiment of the present disclosure will now be described with reference to the accompanying drawings. The semiconductor device according to this embodiment is a high-frequency device provided with a monolithic microwave integrated circuit (MMIC).
As illustrated in
The semiconductor substrate 100 includes a substrate 11 and a semiconductor layer 12. The substrate 11 is formed of, for example, silicon (Si), silicon carbide (SiC), or the like.
The semiconductor layer 12 includes an electron transport layer 12a and a barrier layer 12b. The electron transport layer 12a is formed of gallium nitride (GaN), gallium arsenide (GaAs), or the like and is laminated on the substrate 11. The barrier layer 12b is formed of aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), or the like, and is laminated on the electron transport layer 12a.
The barrier layer 12b has a bandgap larger than that of the electron transport layer 12a and forms a heterojunction structure along with the electron transport layer 12a. In addition, the barrier layer 12b has an implantation layer where impurity atoms (dopant) are implanted. The implantation layer is formed such that a peak of the concentration of the impurity atoms is located in the vicinity of an interface with the electron transport layer 12a, and a part thereof is also formed in the electron transport layer 12a. As a result, a region (2-DEG channel) where a two-dimensional electron gas (2-DEG) is generated is provided in an interface between the electron transport layer 12a and the barrier layer 12b.
The active element 10 is formed in a first region R1 (active element region) of the semiconductor substrate 100. The first region R1 is set as an area for forming the active element 10 in advance. The active element 10 is an element that performs active operation such as amplification or rectification, and specifically includes a transistor, a diode, and the like. The active element 10 of
The passive element 20 is formed in a second region R2 (passive element region) of the semiconductor substrate 100. The second region R2 is set as an area for forming the passive element 20 in advance. The passive element 20 is an element that performs passive operation such as accumulation, consumption, or discharging of the supplied power, and specifically includes a capacitor, a resistor, a coil, and the like. The passive element 20 of
The first insulation film 30 is provided in common with the active element region R1 and the passive element region R2 of the semiconductor substrate 100. The first insulation film 30 covers and protects the active element 10 in the active element region R1. In addition, the first insulation film 30 underlies the passive element 20 in the passive element region R2 to serve as a protection film (passivation film) for protecting the semiconductor substrate 100 (barrier layer 12b) of the passive element region R2. The first insulation film 30 has a thickness so as not to degrade a high-frequency characteristic of the active element 10.
The second insulation film 40 overlies the first insulation film 30 of the passive element region R2. In addition, the second insulation film 40 is not provided over the insulation film 30 of the active element region R1. The second insulation film 40 of
Specifically, the first and second insulation films 30 and 40 are formed of the same insulation material such as silicon nitride (SiN) or silicon dioxide (SiO2) using different formation techniques. For example, the first insulation film 30 is formed using an atomic layer deposition (ALD) technique, and the second insulation film 40 is formed using a plasma chemical vapor deposition (PCVD) technique. Since the ALD and the PCVD are different insulation film formation techniques, the resulting insulation films also have a difference in film quality. As a result, in a case where a predetermined etching process using a liquid or gas is applied to the first and second insulation films 30 and 40, only the second insulation film 40 is removed, and the first insulation film 30 remains.
As described below, the second insulation film 40 is formed in the active element region R1 as well as the passive element region R2 in the course of the manufacturing. However, the second insulation film 40 formed in the active element region R1 is selectively removed (etched). For this reason, a surface of the active element 10 is covered only by the first insulation film 30 as illustrated in
Subsequently, a configuration of the active element 10 (FET) will be descried. The active element 10 is provided in the active element region R1 on the semiconductor substrate 100 and has a dielectric layer 13, a source 14s, a gate 14g, and a drain 14d.
The dielectric layer 13 is formed of an insulation material such as silicon nitride (SiN) or silicon dioxide (SiO2). The dielectric layer 13 is laminated on the semiconductor layer 12 (barrier layer 12b) of the active element region R1.
The gate 14g is interposed between the source 14s and the drain 14d and is provided on the barrier layer 12b. The gate 14g has a contact base portion 141 and a field plate 142.
The contact base portion 141 is provided in the center of the bottom of the gate 14g. The contact base portion 141 is formed on a surface of the barrier layer 12b to make a shottky contact with the barrier layer 12b. Note that a gate insulation film may be formed between the contact base portion 141 and the barrier layer 12b. The contact base portion 141 adjusts a flow of electrons between the source 14s and the drain 14d by controlling a 2-DEG channel provided in an interface between the electron transport layer 12a and the barrier layer 12b.
The field plate 142 is provided to protrude toward the source 14s and the drain 14d from the contact base portion 141 in an eave shape. The dielectric layer 13 is provided between the field plate 142 and the barrier layer 12b to alleviate concentration of electric fields in the contact base portion 141.
The gate 14g is interposed between the source 14s and the drain 14d, and the source 14s and the drain 14d are formed on a surface of the barrier layer 12b to make an ohmic contact with the barrier layer 12b. The source 14s and the drain 14d are provided by interposing the gate 14g and dielectric layer 13.
The surfaces of the dielectric layer 13, the source 14s, the gate 14g, and the drain 14d are covered by the first insulation film 30. That is, the first insulation film 30 provided in the active element region R1 serves as a protection film for protecting the surface of the active element 10.
Meanwhile, the passive element 20 (MIM capacitor) is provided in the passive element region R2 on the semiconductor substrate 100 and has a lower electrode 21 and an upper electrode 22. The first insulation film 30 serving as a passivation film underlies the lower electrode 21. In addition, the second insulation film 40 serving as the interlayer insulation film is provided between the lower electrode 21 and the upper electrode 22.
Manufacturing steps of the semiconductor device 1 configured as described above generally includes the following four steps:
The manufacturing steps of the semiconductor device 1 will now be described details with reference to
As illustrated in
After the first insulation film 30 is formed, the lower electrode 21 of the passive element 20 is patterned in the passive element region R2, for example, through photolithography or the like as illustrated in
After the lower electrode 21 is formed, the second insulation film 40 is formed (second insulation film formation step, step S13 of
Then, the second insulation film 40 formed in the active element region R1 is removed (insulation film exposure step, step S14 of
Then, the upper electrode 22 opposite to the lower electrode 21 is patterned on the second insulation film 40 serving as an interlayer insulation film, for example, through photolithography or the like (step S15 of
Through the aforementioned steps, the semiconductor device 1 of
As described above, according to the present disclosure, the first insulation film 30 is formed using a film formation technique different from that of the second insulation film 40. An etching selectivity between the first and second insulation films 30 and 40 is set such that only the second insulation film 40 is removed, and the first insulation film 30 remains without be removed through the predetermined etching process. For this reason, using the manufacturing steps, the first and second insulation films 30 and 40 can be simultaneously formed in the active element region R1 and the passive element region R2, respectively. Then, the second insulation film 40 formed in the active element region R1 can be selectively removed. As a result, it is possible to form an insulation film (first insulation film 30) that does not degrade the high-frequency characteristic of the active element 10. In addition, it is possible to effectively form the first and second insulation films 30 and 40 of the semiconductor device 1.
Note that an example in which the first insulation film 30 is provided through the ALD technique, and the second insulation film 40 is provided through a PCVD technique has been described in the aforementioned embodiment. However, the etching selectivity between the first and second insulation films 30 and 40 may set such that only the second insulation film 40 is removed, and the first insulation film 30 remains through the etching process. For this reason, any other film formation technique may also be employed in combination. For example, the first insulation film 30 may be formed using a vacuum ALD technique, and the second insulation film 40 may be formed using a vacuum CVD technique or a vacuum physical vapor deposition (PVD) technique. The first and second insulation films 30 and 40 may be formed of different insulation materials using the same or different film formation technique(s) so as to provide the etching selectivity described above.
An example in which the active element 10 is the FET, and the passive element 20 is an MIM capacitor has been described in the aforementioned embodiment. Alternatively, any other active element 10 (such as a diode) or passive element 20 (such as a resistor or a coil) may also be employed.
As illustrated in
While several embodiments have been described hereinbefore, such embodiments are just for illustrative purposes, and are not intended to limit the scope of the invention. Such embodiments may be embodied in various other forms, and various omissions, substitutions, and modification may be possible without departing from the spirit and scope of the invention. Such embodiments and modifications encompass the inventions described in the claims and their equivalents within the sprit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017-007429 | Jan 2017 | JP | national |
