Patent Application
20070293026
Specific embodiments according to the present patent will be described with reference to the accompanying drawings.
From
In contrast, when the furnace type RTP is applied, temperature deviation from the chip patterns is small compared with the lamp type RTP, and the difference in temperature between the wafer edge and the center region is less than 20 degrees Celsius.
In the present invention, the furnace type RTP is employed as an annealing process for activating ions implanted into the source and drain junction so as to reduce the difference in the characteristics of transistors, which is incurred by the pattern effect. It is noted that a lamp or line type RTP may be performed instead of the furnace type RTP.
The annealing is performed in a state where the temperature at the top, top corners and sidewalls of the annealing chamber are set differently (a state where the temperature gradient is different) at the time of annealing.
Referring to
Thus, if the furnace type RTP having a temperature gradient is performed as the annealing process for activating ions implanted into the source and drain junction, the source and drain junction of transistors formed in the wafer center region diffuses more into the junction than transistors formed on the wafer edge. Consequently, the on current of a transistor in the wafer center region increases, and the threshold voltage rises.
Since the threshold voltage of transistors in the center region rises, which had relatively lower threshold voltage than that of the wafer edge region, it is therefore possible to decrease threshold voltage deviation throughout the wafer.
The temperature gradient is not limited to a temperature on a chamber-region basis, proposed in the present invention, but may be implemented differently depending on the process step. For example, the temperature at the top of the chamber may be set lower than that at the top corners of the chamber, and the temperature at the top corners of the chamber may be set lower than that at the sidewalls of the chamber. In other words, the temperature at the top, top corners and sidewalls of the annealing chamber may be set differently.
Referring to
A gate oxide layer 41 and a polysilicon layer are sequentially deposited. The polysilicon layer and the gate oxide layer 41 are patterned to form a gate 43 on a specific region. The gate 43 has a structure in which the gate oxide layer 41 and a gate electrode 42 are laminated.
The gate oxide layer 41 is formed by a wet oxidization process in the temperature range of 70 to 800 degrees Celsius. The polysilicon layer is formed using a doped polysilicon layer having a minimum grain size by using SiH4 or a mixed gas of Si2H6 and PH3 by means of a Low Pressure Chemical Vapor Deposition (LPCVD).
An insulating layer (e.g., a Hot Temperature Oxide (HTO) layer) is formed on the entire surface including the gate 43. A spacer 44 is formed on both sides of the gate 43 by performing a blanket etch. The HTO layer may be formed by LPCVD in the pressure range of 1 to 3 Torr and a temperature range of 650 to 800 degrees Celsius.
Referring to
In the case where BF2 is used, an ion implantation energy of 1 to 30 KeV and an ion implantation dose of 1E14 to 5E15 ions/cm2 are used. In the case where the mixed ion of B and BF2 is used, BF2 is implanted with ion implantation energy of 1 to 30 KeV and a dose of 1E14 to 3E15 ions/cm2. B is implanted with an ion implantation energy of 1 to 20 KeV and an ion implantation dose of 1E14 to 3E15 ions/cm2.
BF2 has a high atomic weight and is thus effective in forming a shallow junction. The mixed ion of BF2 and B is effective in prohibiting the occurrence of defects due to an inert dopant.
Referring to
If the furnace type RTP is used as described above, the pattern effect can be reduced, and deviation in the characteristic of transistors due to the pattern effect can be improved.
Meanwhile, if a p type dopant is implanted as the threshold voltage ion, the threshold voltage of the transistors formed in the wafer center region is low, and the threshold voltage of the transistors formed in the edge region is high. In the furnace type RTP, the temperature gradient is higher in the center region than in the wafer edge region, so that the low threshold voltage of transistors located in the center region can be raised.
Furthermore, the present invention may be applied to an annealing process other than the source/drain junction formation process. As a result, the uniformity of transistor threshold voltages across a single wafer is improved. Accordingly, semiconductor devices can be fabricated stably.
As described above, the present invention has one of more of the following advantages.
The furnace type RTP is used as an annealing process for activating ions implanted into the source and drain junction. Accordingly, the pattern effect can be minimized, and deviation in the characteristic of transistors due to the pattern effect can be improved.
Annealing is performed with temperature gradient. Accordingly, variation in the threshold voltage of the wafer edge region and the wafer center region can be improved, and the uniformity of the threshold voltage can be obtained.
An increase in the uniformity of a single wafer, which becomes serious as the size of the wafer increases, can be solved by simple tuning the annealing method.
Devices can be stably fabricated by actively coping with the short channel effect in which the transistor characteristic is changed a lot by means of a subsequent process of a high temperature
The above embodiments of the present invention are illustrative and various alternatives and modifications are possible in view of the present disclosure and are intended to fall within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-54420 | Jun 2006 | KR | national |
| 2006-96002 | Sep 2006 | KR | national |
