Patent Application
20240297145
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-031384, filed Mar. 1, 2023, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally
to a method of manufacturing a semiconductor device.
A three-dimensional stacking technique for three-dimensionally stacking semiconductor circuit substrates is known.
example of a configuration of a semiconductor device having a bonding structure.
an example of a cross-sectional structure in a manufacturing process of the semiconductor device according to the first embodiment.
In general, according to one embodiment, a method of manufacturing a semiconductor device in which a first substrate and a second substrate on which a first circuit layer and a second circuit layer different from each other are formed, respectively are bonded, the method includes: forming, on the first substrate, a first layer having a refractive index lower than a refractive index of the first substrate; forming, on the first layer, a second layer having a refractive index lower than a refractive index of the first layer; forming the first circuit layer on the second layer; bonding a front surface of the first substrate and a front surface of the second substrate after forming the first circuit layer;
irradiating a back surface of the first substrate with a laser beam after bonding the first substrate and the second substrate; and peeling the first substrate so that the first circuit layer remains on a side of the second substrate after irradiating the back surface of the first substrate with the laser beam.
Hereinafter, each embodiment will be described with reference to the drawings. Each embodiment exemplifies an apparatus and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual. Dimensions, ratios, and the like in each drawing are not necessarily the same as actual ones. The illustration of configurations is omitted as appropriate. Hatching added to plan views is not necessarily related to the materials and properties of constituent elements. In the present specification, constituent elements having substantially the same function and configuration are denoted by the same reference signs. Numbers, characters, and the like added to reference signs are referred to by the same reference signs and are used to distinguish between similar elements.
First, an outline of a process of reusing a wafer will be described.
In a manufacturing process of the semiconductor device, first, a combination of the first wafer W1 and the second wafer W2 is prepared (“wafer allocation”). In the present example, each of the first wafer W1 and the second wafer W2 is a silicon substrate. The first wafer W1 is used for forming a first semiconductor circuit. The second wafer W2 is used for forming a second semiconductor circuit different from the first semiconductor circuit. The semiconductor device is configured to function using a combination of the first semiconductor circuit and the second semiconductor circuit. The design of each of the first semiconductor circuit and the second semiconductor circuit can be appropriately changed according to the function of the semiconductor device.
Next, the first semiconductor circuit is formed on the first wafer W1 by a front-end process of each of the first wafer W1, and the second semiconductor circuit is formed on the second wafer W2 by a front-end process of the second wafer W2. In addition, a layer for achieving the process of reusing a wafer is formed before the formation of the first semiconductor circuit. Specifically, a peeling layer 100, a circuit layer 200, and a bonding layer B1 are sequentially formed on the first wafer W1. The peeling layer 100 is a layer used as a starting point for separating the first semiconductor circuit formed on the first wafer W1 from the first wafer W1. The peeling layer 100 includes a material (for example, a silicon oxide film) having a property of absorbing a laser beam used in peeling process to be described later. The circuit layer 200 is a layer including the first semiconductor circuit. The bonding layer B1 is a layer including a bonding pad used for connection with the first semiconductor circuit formed on the first wafer W1. A circuit layer 300 and a bonding layer B2 are sequentially formed on the second wafer W2. The circuit layer 300 is a layer including the second semiconductor circuit. The bonding layer B2 is a layer including a bonding pad used for connection with the bonding pad formed on the bonding layer B1.
Next, the bonding process of the first wafer W1 and the second wafer W2 is executed. Specifically, a bonding device disposes a front surface of the first wafer W1 and a front surface of the second wafer W2 to face each other. Then, the bonding device adjusts an overlapping position of a pattern formed on the front surface of the first wafer W1 and a pattern formed on the front surface of the second wafer W2 and bonds the front surface of the first wafer W1 and the front surface of the second wafer W2 to each other. As a result, the bonding layer B1 of the first wafer W1 and the bonding layer B2 of the second wafer W2 are bonded, and the first semiconductor circuit provided on the first wafer W1 and the second semiconductor circuit provided on the second wafer W2 are electrically connected.
Next, the peeling process of the first wafer W1 is executed. In the peeling process in the present specification, a peeling method using the laser beam is used. Specifically, first, a back surface of the first wafer W1 is irradiated with the laser beam. Then, a crack is generated from a peripheral edge portion between the first wafer W1 and the second wafer W2 that are bonded. Then, the first wafer W1 is peeled with the peeling layer 100 as a starting point. As a result, a structure in which the circuit layer 300, the bonding layer B2, the bonding layer B1, and the circuit layer 200 are sequentially stacked on the second wafer W2 remains. The peeled first wafer W1 is reused (“wafer reuse”) after surface processing such as removal of a residual film is executed.
Thereafter, an interconnect process is executed with respect to the second wafer W2. The interconnect process includes, for example, a process of forming a pad used for connection between the first semiconductor circuit and/or the second semiconductor circuit and an external device, a process of forming a pad for supplying power to the semiconductor device, and the like. After the interconnect process is completed, the second wafer W2 is separated into chip units by dicing process. As a result, the semiconductor device having a bonding structure is formed. Note that in the present specification, a case where the semiconductor device is formed using two wafers is exemplified, but the present invention is not limited to this. The number of wafers used for forming the semiconductor device may be three or more. In other words, the semiconductor device may have a bonding structure using a total of three or more wafers.
In the peeling process of the first wafer W1, the back surface of the first wafer W1 is irradiated with the laser beam LB at a predetermined interval. As the laser beam LB, for example, a CO2 laser having a wavelength of 9.3 micrometers (μm) is used. The CO2 laser has a property of passing through the silicon substrate and being absorbed by the silicon oxide film. In other words, the transmittance of the first wafer W1 with respect to the laser beam LB is higher than the transmittance of the silicon oxide film with respect to the laser beam LB. Note that the laser beam LB incident on the peeling layer 100 is influenced by interference of a reflected light beam at an interface between the first wafer W1 and the peeling layer 100. Therefore, a light absorption rate of the peeling layer 100 with respect to the laser beam LB changes according to the thickness of the first wafer W1.
In a case where the laser beam LB emitted to the back surface of the first wafer W1 passes through the first wafer W1 and is emitted to the silicon oxide film included in the peeling layer 100, the silicon oxide film absorbs the laser beam LB to generate heat. Then, the heat generated in the peeling layer 100 propagates to a vicinity of the interface between the first wafer W1 and the peeling layer 100. As a result, a portion of the first wafer W1 in the vicinity of the interface with the peeling layer 100 is plastically deformed according to the propagated heat. The interface between the plastically deformed first wafer W1 and the peeling layer 100 is more easily peeled than before the irradiation of the laser beam LB. As a result, in the peeling process, the first wafer W1 and the peeling layer 100 can be peeled with a space between the first wafer W1 and the peeling layer 100 as a peeling surface.
A method of manufacturing a semiconductor device 1 according to a first embodiment suppresses fluctuations in a light absorption rate of a peeling layer 100 with respect to a laser beam LB emitted to a back surface of a first wafer W1 by inserting an antireflection layer 110 into the peeling layer 100. Hereinafter, details of the first embodiment will be described.
First, a configuration of the semiconductor device 1 according to the first embodiment will be described. In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. An X direction and a Y direction are directions intersecting each other and parallel to a front surface of a wafer. A Z direction is a direction intersecting with each of the X direction and the Y direction and corresponds to a vertical direction with respect to the front surface of the wafer (substrate). In the present specification, “up and down” is defined based on a direction along the Z direction. In addition, in the present specification, a direction away from a front surface side of the substrate as a reference is defined as a positive direction (upward).
In the peeling layer 100, the antireflection layer 110 is provided on the first wafer W1. The light absorption layer 120 is provided on the antireflection layer 110. The circuit layer 200 is provided on the light absorption layer 120. A refractive index of the antireflection layer 110 is a value between a refractive index of the first wafer W1 and a refractive index of the light absorption layer 120. In other words, in the first embodiment, the antireflection layer 110 having a refractive index between the refractive index of the first wafer W1 and the refractive index of the light absorption layer 120 is inserted into an interface between the first wafer W1 and the light absorption layer 120 (peeling layer 100). The antireflection layer 110 is configured to reduce the intensity of a reflected light beam from the interface between the first wafer W1 and the light absorption layer 120.
As the light absorption layer 120, for example, a silicon oxide film is used. Note that it suffices that the light absorption layer 120 is configured so that the transmittance of the first wafer W1 with respect to the laser beam LB is higher than the transmittance of the light absorption layer 120 with respect to the laser beam LB. The antireflection layer 110 may be a layer in which the same member (medium) as the light absorption layer 120 and another member (medium) are patterned and mixed. In other words, the antireflection layer 110 may include a homogeneous medium having a refractive index between the refractive index of the first wafer W1 and the refractive index of the light absorption layer 120. Each of the antireflection layer 110 and the light absorption layer 120 may be referred to as an “interlayer film”.
The circuit layer 300 and the bonding layer B2 are formed on the second wafer W2 (S10). The processing of S10 corresponds to a front-end process of the second wafer W2. In addition, the antireflection layer 110 is formed on the first wafer W1 (S11). Next, the light absorption layer 120 is formed on the antireflection layer 110 (S12). Next, the circuit layer 200 and the bonding layer B1 are formed above the light absorption layer 120 (S13). The processing of S11 to S13 corresponds to a front-end process of the first wafer W1. The processing of S10 and the processing of S11 to S13 may be executed in parallel, or the order of these processing processes may be switched.
Next, the bonding process of the first wafer W1 and the second wafer W2 is executed (S14) . Through the processing of S14, the bonding layer B1 formed on the first wafer W1 and the bonding layer B2 formed on the second wafer W2 are bonded, and a first semiconductor circuit included in the circuit layer 200 and a second semiconductor circuit included in the circuit layer 300 are electrically connected.
Next, as illustrated in
Next, the first wafer W1 is peeled (S16). Through the processing of S16, the first wafer W1 is peeled with a space between the antireflection layer 110 and the first wafer W1 as a peeling surface, and a structure in which the circuit layer 300 and the circuit layer 200 remain is formed on the second wafer W2. Next, the antireflection layer 110 and the light absorption layer 120 are removed (S17). In the processing of S17, part of the circuit layer 200 may be removed. Next, the interconnect layer 400 is formed (S18). In the processing of S18, the plurality of pads PD connected to either of the first semiconductor circuit included in the circuit layer 200 and the second semiconductor circuit included in the circuit layer 300 is formed on the surface of the semiconductor device 1. As a result, a structure of the semiconductor device 1 illustrated in
Hereinafter, a method for optimizing design parameters of the peeling layer 100 in the semiconductor device 1 according to the first embodiment will be described with reference to
In the present example, the antireflection layer 110 is a film having a refractive index of 2.5. In addition, the thickness of the antireflection layer 110 is set to 0.1 μm. Hereinafter, the thickness of the first wafer W1 is referred to as “wafer thickness”, the thickness of the silicon oxide film OX is referred to as “oxide film thickness H0”, and the thickness of the antireflection layer 110 is referred to as “antireflection layer thickness H1”.
In the case of optimizing the design parameters of the peeling layer 100, first, the fluctuation range and the average value of the light absorption rate in a case where respective conditions of the oxide film thickness H0 and the antireflection layer thickness H1 are changed are evaluated. As an evaluation result of the fluctuation range of the light absorption rate in the present example, the simulation result as illustrated in
In the case of optimizing the design parameters, a threshold value or a range may be set in advance for each of the oxide film thickness H0 and the antireflection layer thickness H1. In addition, a value such that the fluctuation range of the light absorption rate becomes small and the average value of the light absorption rate becomes large may be calculated based on a formula illustrating the fluctuation range of the light absorption rate and a formula illustrating the average value of the light absorption rate. In the processing of each of S11 and S12 illustrated in
The method of manufacturing the semiconductor device 1 according to the first embodiment described above can suppress a manufacturing cost of a semiconductor device 1. Hereinafter, details of effects of the first embodiment will be described.
As a method of manufacturing a semiconductor device having a bonding structure, there is known a method in which a first wafer W1 is bonded to a second wafer W2, and then the first wafer W1 is removed by a back grinding (back surface cutting) processing or the like. Meanwhile, if the first wafer W1 after the bonding can be reused for manufacturing another semiconductor device, it is possible to suppress wastewater treatment and a wafer cost associated with back grinding processing and the like. Therefore, there is studied “laser peeling” in which the peeling layer 100 is formed before the first semiconductor circuit is formed on the first wafer W1, and the peeling process with the peeling layer 100 as a starting point is executed by laser irradiation.
In the laser peeling, for example, the silicon oxide film included in the peeling layer 100 is heated by the laser beam LB, whereby the vicinity of the interface between the first wafer W1 and the peeling layer 100 is plastically deformed. Then, a crack is caused to occur on the bonding surface of the first wafer W1 and the second wafer W2, whereby the first wafer W1 can be peeled with the peeling layer 100 as a starting point. However, in the laser peeling, the light absorption rate in the peeling layer 100 changes due to an interference effect of the reflected light beam at the back surface of the first wafer W1 (interface with air) and a reflected light beam at an interface between the first wafer W1 and the peeling layer 100. In other words, the light absorption rate of the peeling layer 100 fluctuates according to a magnitude of the interference effect of these light beams. For example, the magnitude of the interference effect of the light beams changes according to the wafer thickness. In the laser peeling, a stable peeling process becomes possible by causing the peeling layer 100 to absorb specified power. In other words, fluctuations in the light absorption rate can be a factor for the peeling process of the first wafer W1 by the laser peeling to be unstable.
Here, a factor of the change in the light absorption rate according to the wafer thickness will be described.
In the comparative example, if the back surface of the first wafer W1 is irradiated with a CO2 laser of non-polarization (wavelength: 9.2 to 10.8 μm), for example, three types of reflected light beams RP1 to RP3 are generated. The reflected light beam RP1 corresponds to a light beam that is the CO2 laser is reflected at an interface between air and the first wafer W1. The intensity of the reflected light beam RP1 is large because a refractive index difference between air and silicon is large. The reflected light beam RP2 corresponds to a light beam reflected at an interface between the first wafer W1 and the silicon oxide film OX. The intensity of the reflected light beam RP2 is large because a refractive index difference between silicon and the silicon oxide film OX is large. The reflected light beam RP3 corresponds to a light beam reflected at an interface between the silicon oxide film OX and the second wafer W2. The intensity of the reflected light beam RP3 is small because the intensity of the reflected light beam RP3 is influenced by absorption by the silicon oxide film OX. Therefore, in the comparative example, an interference effect of the reflected light beams RP1 and RP2 becomes relatively large.
In contrast to this, the semiconductor device 1 according to the first embodiment has a configuration in which the antireflection layer 110 is inserted into the interface between the first wafer W1 and the silicon oxide film OX.
RP2 with respect to the structure used in the first embodiment illustrated in
In the first embodiment, if the back surface of the first wafer W1 is irradiated with a CO2 laser of non-polarization (wavelength: 9.2 to 10.8 μm), the reflected light beam RP1 similar to that in the comparative example is generated. In the first embodiment, the reflected light beam RP2 described in the comparative example is divided into two reflected light beams RP2a and RP2b. Specifically, the reflected light beam RP2a corresponds to a light beam reflected at an interface between the first wafer W1 and the antireflection layer 110. The reflected light beam RP2b corresponds to a light beam reflected at an interface between the antireflection layer 110 and the silicon oxide film OX. The sum of the intensities of the reflected light beams RP2a and RP2b is reduced as compared with that of the reflected light beam RP2 in the comparative example because each of a refractive index difference at the interface between the first wafer W1 and the antireflection layer 110 and a refractive index difference at the interface between the antireflection layer 110 and the silicon oxide film OX are smaller than a refractive index difference in the case of the reflected light beam RP2 in the comparative example. In addition, in the first embodiment, the phases of the reflected light beams RP2a and RP2b are shifted according to the thickness of the antireflection layer 110. As a result, in the first embodiment, the fluctuation range due to interference by the reflected light beams RP1 and RP2 can be reduced as compared with the comparative example.
As described above, the method of manufacturing the semiconductor device 1 according to the first embodiment can suppress fluctuations in the light absorption rate based on fluctuations in the wafer thickness in a peeling process of the first wafer W1 using the laser peeling. In other words, the method of manufacturing the semiconductor device 1 according to the first embodiment can suppress fluctuations in energy absorbed by the peeling layer 100 in the laser peeling and can achieve a stable peeling process. As a result, the method of manufacturing the semiconductor device 1 according to the first embodiment can improve a yield of a manufacturing process of a semiconductor device that reuses the first wafer W1, and the method can suppress a manufacturing cost of the semiconductor device.
A method of manufacturing a semiconductor
device 1 according to a second embodiment uses an antireflection layer 110a including a homogeneous medium to suppress fluctuations in a light absorption rate of a peeling layer 100 with respect to a laser beam LB emitted to a back surface of a first wafer W1. Hereinafter, details of the second embodiment will be described mainly on differences from the first embodiment.
First, a configuration of the semiconductor device 1 according to the second embodiment will be described. The semiconductor device 1 according to the second embodiment has a configuration similar to the configuration of the first embodiment except that a structure of the peeling layer 100 formed in a manufacturing process is different. Hereinafter, the peeling layer 100 formed in the manufacturing process of the semiconductor device 1 according to the second embodiment is referred to as a “peeling layer 100a”.
Each of
As illustrated in
100
a has a plurality of antireflection layers 110a in a plan view. Each of the plurality of antireflection layers 110a has, for example, a portion provided while extending along a Y direction. The portion of each antireflection layer 110a provided while extending along the Y direction is disposed in a line-and-space pattern shape in a plan view, that is, at a substantially equal interval. In the present example, a light absorption layer 120 is provided in a portion corresponding to a space between the plurality of the antireflection layers 110a disposed in the line-and-space pattern.
As illustrated in
Hereinafter, a width of a line portion in a pattern formed in a line-and-space pattern shape is referred to as a “line width”, and a width of a space portion is referred to as a “space width”. A pitch at which the line portions of the plurality of antireflection layers 110a disposed in the line-and-space pattern are disposed is referred to as a “main pitch P1”. The main pitch P1 is designed to have dimensions based on a wavelength of the laser beam LB. Specifically, the main pitch P1 is designed to be one fifth or less of the wavelength of the laser beam LB. In addition, a pitch at which the line portions of the plurality of sub-patterns 111 disposed in a line-and-space pattern shape are disposed is referred to as a “sub-pitch P2”. The sub-pitch P2 is designed to be narrower than the main pitch P1. Furthermore, the sub-pitch P2 is designed to have dimensions such that each antireflection layer 110a does not overlap an adjacent antireflection layer 110a according to the number of sub-patterns 111 included in each antireflection layer 110a.
As described above, in the peeling layer 100a, the antireflection layer 110a is provided with a structure having a period (main pitch P1) sufficiently shorter than the wavelength of the laser beam LB. Therefore, a set of the antireflection layer 110a and the light absorption layer 120 at a height at which the antireflection layer 110a is provided can be regarded as a homogeneous medium (that is, a uniform film) for the laser beam LB based on an effective medium approximation (EMA) theory. The EMA theory is an analytical theory for regarding a structure having a period sufficiently shorter than a wavelength as a homogeneous medium. As one of the simplest models of EMA, there is known a linear EMA model that calculates an equivalent refractive index n and an extinction coefficient k from a volume ratio of a medium. In the second embodiment, the above-described homogeneous medium is designed to have a refractive index between a refractive index of the first wafer W1 and a refractive index of the light absorption layer 120.
Note that the peeling layer 100a may have a configuration such that the disposition of the plurality of antireflection layers 110a illustrated in
In the peeling layer 100a, the plurality of antireflection layers 110a is provided on the first wafer W1. The light absorption layer 120 has a portion provided on the first wafer W1 and portions provided on an upper surface and a side surface of the antireflection layer 110a. In other words, the light absorption layer 120 is provided so as to cover a side surface and an upper surface of each of the plurality of antireflection layers 110a. In the second embodiment, the homogeneous medium including the plurality of antireflection layers 110a and a part of the light absorption layer 120 is inserted into an interface between the first wafer W1 and the light absorption layer 120. In other words, in a layer at a height at which the antireflection layer 110a is provided, the plurality of antireflection layers 110a and the light absorption layer 120 are configured to reduce the intensity of a reflected light beam from the interface between the first wafer W1 and the light absorption layer 120. As the antireflection layer 110a, for example, polysilicon is used. The antireflection layer 110a may be referred to as a “member”. In the peeling layer 100a, each of oxide film thickness H0 and antireflection layer thickness H1 is designed to suppress fluctuations in a light absorption rate.
As illustrated in (1) of
<2-2> Method of Manufacturing
of a method of manufacturing the semiconductor device 1 according to the second embodiment. As illustrated in
Specifically, first, similarly to the first embodiment, the processing of S10 and S11 is sequentially executed. In other words, a circuit layer 300 and a bonding layer B2 are formed on the second wafer W2 (S10). The antireflection layer 110a is formed on the first wafer W1 (S11).
Then, the antireflection layer 110a is processed into a line-and-space pattern shape (S20). In the processing of S20, the antireflection layer 110a is processed into a shape of the antireflection layer 110a illustrated in
Thereafter, similarly to the first embodiment, the processing of S13 to S18 are sequentially executed to form a structure of the semiconductor device 1 illustrated in
As described above, in the method of manufacturing the semiconductor device 1 according to the second embodiment, the fluctuations in the light absorption rate based on fluctuations in the wafer thickness can be suppressed in a peeling process of the first wafer W1 using laser peeling, as compared with the first embodiment. In other words, the method of manufacturing the semiconductor device 1 according to the second embodiment can suppress fluctuations in energy absorbed by the peeling layer 100a in the laser peeling and can achieve a stable peeling process, as compared with the first embodiment. As a result, the method of manufacturing the semiconductor device 1 according to the second embodiment can improve a yield of a manufacturing process of a semiconductor device that reuses the first wafer W1, and the method can suppress a manufacturing cost of the semiconductor device.
A third embodiment relates to a method of manufacturing a semiconductor device 1 that suppresses fluctuations in a light absorption rate with a combination of a peeling layer 100a similar to the peeling layer 100a of the second embodiment and polarization of a laser beam LB. Hereinafter, details of the third embodiment will be described mainly on differences from the first and second embodiments.
A configuration of the semiconductor device 1 according to the third embodiment is similar to the configuration of the semiconductor device 1 according to the second embodiment. In addition, similarly, a structure of the peeling layer 100a formed in a manufacturing process of the semiconductor device 1 according to the third embodiment is also similar to the structure of the peeling layer 100a formed in the manufacturing process of the semiconductor device 1 according to the second embodiment.
of the method of manufacturing the semiconductor device 1 according to the third embodiment. As illustrated in
Specifically, first, similarly to the second embodiment, the processing of S10, S11, S20, S21, S13, and S14 is sequentially executed. In other words, a circuit layer 300 and a bonding layer B2 are formed on the second wafer W2 (S10). The antireflection layer 110a is formed on the first wafer W1 (S11). The antireflection layer 110a is processed into a line-and-space pattern shape (S20). A light absorption layer 120 is formed on the first wafer W1 and the processed antireflection layer 110a (S21). Next, a circuit layer 200 and a bonding layer B1 are formed above the light absorption layer 120 (S13). The bonding process of the first wafer W1 and the second wafer W2 is executed (S14).
Then, a back surface of the first wafer W1 is irradiated with a laser beam LBa of polarization orthogonal to a pattern or a laser beam LBb of polarization parallel to the pattern with respect to the antireflection layer 110a in the line-and-space pattern shape (S30). The polarization orthogonal to the pattern is polarization orthogonal to a line-and-space pattern. The polarization parallel to the pattern is polarization parallel to the line-and-space pattern. In the processing of S30, the laser beam LBa or LBb passes through the first wafer W1 and reaches the peeling layer 100a including the antireflection layer 110a and the light absorption layer 120. At this time, the light absorption layer 120 absorbs the laser beam LBa or LBb at a light absorption rate corresponding to an interference effect of a reflected light beam at the back surface of the first wafer W1 (interface with air), a reflected light beam at an interface between the first wafer W1 and the peeling layer 100a (that is, an upper end portion of the antireflection layer 110a), and a reflected light beam at a lower end portion of the antireflection layer 110a. Then, the light absorption layer 120 generates heat by absorbing the laser beam LBa or LBb, and a vicinity of a portion in contact with a peeling surface of the first wafer W1 is plastically deformed based on the heat generated in the light absorption layer 120. Then, an irradiation position of the laser beam LBa or LBb is changed, and the back surface of the first wafer W1 is irradiated with the laser beam LBa or LBb at a predetermined interval.
Thereafter, similarly to the first embodiment, the processing of S16 to S18 is sequentially executed to form a structure of the semiconductor device 1 illustrated in
LB is polarization parallel to the line-and-space pattern of the antireflection layer 110a or polarization orthogonal to the line-and-space pattern of the antireflection layer 110a in the case of irradiating the back surface of the first wafer W1 with the laser beam LB. Other methods of manufacturing the semiconductor device 1 according to the third embodiment are similar to the method of manufacturing the semiconductor device 1 according to the second embodiment.
As illustrated in
As described above, the method of manufacturing the semiconductor device 1 according to the third embodiment may be able to suppress fluctuations in the light absorption rate based on fluctuations in the wafer thickness in a peeling process of the first wafer W1 using laser peeling, as compared with the case of the non-polarization. In other words, the method of manufacturing the semiconductor device 1 according to the third embodiment can suppress fluctuations in energy absorbed by the peeling layer 100a in the laser peeling by using appropriate polarization and can achieve a stable peeling process, as compared with the second embodiment. As a result, the method of manufacturing the semiconductor device 1 according to the third embodiment can improve a yield of a manufacturing process of a semiconductor device that reuses the first wafer W1, and the method can suppress a manufacturing cost of the semiconductor device.
A fourth embodiment is a specific example of a semiconductor device 1 to which any of the first to third embodiments is applied. Hereinafter, as the fourth embodiment, a case where the above-described embodiment and a memory device capable of storing data in a non-volatile manner are combined will be described.
The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (“n” is an integer of 1 or more). A block BLK is a set of a plurality of memory cells. The block BLK corresponds to, for example, a unit of erasing data. The block BLK includes a plurality of pages. The page corresponds to a unit in which read and write of data are executed. Although not illustrated, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm (“m” is an integer of 1 or more) and a plurality of word lines WL. Each memory cell is associated with, for example, one bit line BL and one word line WL.
The input/output circuit 11 is an interface circuit that controls transmission and reception of an input/output signal from and to the memory controller 2. The input/output signal includes, for example, data DAT, status information, address information, a command, and the like. The input/output circuit 11 can input and output the data DAT from and to the sense amplifier module 17 and from and to the memory controller 2. The input/output circuit 11 can output the status information transferred from the register circuit 13 to the memory controller 2. The input/output circuit 11 can output each of the address information and the command transferred from the memory controller 2 to the register circuit 13.
The logic controller 12 controls each of the input/output circuit 11 and the sequencer 14 based on a control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the semiconductor device 1a. The logic controller 12 notifies the input/output circuit 11 that the input/output signal received by the input/output circuit 11 is a command, address information, or the like. The logic controller 12 orders the input/output circuit 11 to input or output the input/output signal.
The register circuit 13 temporarily stores the status information, the address information, and the command. The status information is updated based on the control of the sequencer 14 and transferred to the input/output circuit 11. The address information includes a block address, a page address, a column address, and the like. The command includes an order related to various operations of the semiconductor device 1a.
The sequencer 14 controls the entire operation of the semiconductor device 1a. The sequencer 14 executes a read operation, a write operation, an erase operation, and the like based on the command and the address information stored in the register circuit 13.
The driver circuit 15 generates a voltage used for the read operation, the write operation, the erase operation, and the like. Then, the driver circuit 15 supplies the generated voltage to the row decoder module 16, the sense amplifier module 17, and the like.
The row decoder module 16 is a circuit used for selecting the block BLK to be operated and transferring a voltage to an interconnect such as the word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively. Each row decoder RD is used for selecting the block BLK.
The sense amplifier module 17 is a circuit used for transferring a voltage to each bit line BL and reading data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with the plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier for determining data and a latch circuit for temporarily holding data.
A circuit layer 200 in the semiconductor device 1a includes, for example, the memory cell array 10. A circuit layer 300 in the semiconductor device 1a includes, for example, the input/output circuit 11, the logic controller 12, the register circuit 13, the sequencer 14, the driver circuit 15, the row decoder module 16, and the sense amplifier module 17. Note that a combination of the semiconductor device 1a and the memory controller 2 may constitute one semiconductor device. An example of such a semiconductor device include a memory card such as an SDTM card, a solid state drive (SSD), and the like.
The bit lines BL0 to BLm and a source line SL are shared by the plurality of blocks BLK.
Each string unit SU includes a plurality of NAND strings NS. Each of the plurality of NAND strings NS is associated with each of the bit lines BL0 to BLm. That is, each bit line BL is shared by the NAND string NS to which the same column address among the plurality of blocks BLK is allocated. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell including a control gate and a charge storage layer and holds (stores) data in a nonvolatile manner. Each of the select transistors ST1 and ST2 is used for selecting the string unit SU.
In each NAND string NS, the select transistor ST1, the memory cell transistors MT0 to MT7, and the select transistor ST2 are connected in series in this order. Specifically, a drain of the select transistor ST1 is connected to the associated bit line BL, and a source of the select transistor ST1 is connected to a drain of the memory cell transistor MT7. A drain of the select transistor ST2 is connected to a source of the memory cell transistor MT0, and a source of the select transistor ST2 is connected to the source line SL. The memory cell transistors MT0 to MT7 are connected in series between the select transistors ST1 and ST2.
The select gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each select gate line SGD is connected to a gate of each of a plurality of select transistors ST1 included in the associated string unit SU. The select gate line SGS is connected to a gate of each of a plurality of select transistors ST2 included in an associated block BLK. The word lines WL0 to WL7 are connected to the control gates of the memory cell transistors MT0 to MT7, respectively.
A set of a plurality of memory cell transistors MT connected to a common word line WL in the same string unit SU is referred to as, for example, a “cell unit CU”. For example, a storage capacity of the cell unit CU in a case where each memory cell transistor MT stores 1-bit data is defined as “1-page data”. The cell unit CU can have a storage capacity of 2-page or more data according to the number of bits of data stored in each memory cell transistor MT.
Note that the circuit configuration of the memory cell array 10 included in the semiconductor device 1a may be another configuration. For example, the number of string units SU included in each block BLK, the number of memory cell transistors MT included in each NAND string NS, the number of select transistors ST1 included in each NAND string NS, and the number of select transistors ST2 included in each NAND string NS can be designed to be any numbers.
Hereinafter, a structure of the semiconductor device 1a according to the fourth embodiment will be described.
Each slit SLT has a portion provided while extending along the X direction and crosses the hookup region HR1, the memory region MR, and the hookup region HR2 along the X direction. The plurality of slits SLT is arranged in a Y direction. Each slit SLT divides interconnects (for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS) adjacent to each other via the slit SLT. In each slit SLT, a conductor in which a spacer of an insulator is provided on a side wall may be disposed while being insulated from these interconnects or an insulator may be embedded. In the memory cell array 10, each region divided along the Y direction by the slit SLT corresponds to one block BLK.
Each slit SHE has a portion provided while extending along the X direction and crosses the memory region MR along the X direction. The plurality of slits SHE is arranged in the Y direction. In the present example, four slits SHE are disposed between each set of two slits SLT adjacent to each other in the Y direction. Each slit SHE has, for example, a structure in which an insulator is embedded. Each slit SHE divides interconnects adjacent to each other via the slit SHE. It suffices that the slit SHE divides at least the select gate line SGD. In the memory cell array 10, each region divided along the Y direction by the slits SLT and SHE corresponds to one string unit SU.
Each end of the stack interconnect (for example, the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD) included in the memory cell array 10 has a terrace portion in each of the hookup regions HR1 and HR2. The terrace portion corresponds to a portion that does not overlap the interconnect layer (conductive layer) provided on a side of the bit line BL. A structure formed by a plurality of terrace portions is similar to a step, a terrace, rimstone, or the like. In the present example, a staircase structure having a step in the X direction is formed by an end of the select gate line SGS, an end of each of the word lines WL0 to WL7, and an end of the select gate line SGD.
The contact CC connected to the stack interconnect is connected to the terrace portion of at least one of the hookup regions HR1 and HR2. For example, the stack interconnect of the even-numbered block BLK (BLK0, BLK2, . . . ) is connected to the contact CC provided in the hookup region HR1. The stack interconnect of the odd-numbered block BLK (BLK1, BLK3, . . . ) is connected to the contact CC provided in the hookup region HR2.
Note that the planar layout of the memory cell array 10 included in the semiconductor device 1a may be another layout. For example, the number of slits SHE disposed between two slits SLT adjacent to each other can be designed to be any number. The number of string units SU included in each block BLK can be changed based on the number of slits SHE disposed between two slits SLT adjacent to each other. The disposition of the contact CC connected to the stack interconnect can be appropriately changed. The semiconductor device 1a may have a structure in which the terrace portion of each hookup region HR is omitted. In this case, the contact CC connected to a certain interconnect layer of the stack interconnect penetrates an upper conductive layer and is provided while being separated (insulated). The hookup region HR may be disposed so as to divide the memory region MR in the X direction.
Each memory pillar MP functions as one NAND string NS. The plurality of memory pillars MP is disposed, for example, in a staggered manner with 24 rows in a region between two slits SLT adjacent to each other. In the present example, one slit SHE is disposed while overlapping each of the memory pillar MP in the fifth row, the memory pillar MP in the 10th row, the memory pillar MP in the 15th row, and the memory pillar MP in the 20th row if counted from the upper side of the paper surface.
Each of the bit lines BL has a portion provided while extending in the Y direction. The plurality of bit lines BL is arranged in the X direction. Each bit line BL is disposed so as to overlap at least one memory pillar MP for each string unit SU. In the present example, two bit lines BL are disposed while overlapping one memory pillar MP. The memory pillar MP is electrically connected to one bit line BL via the contact CV.
The contact LI is a conductor having a portion provided while extending in the X direction. The spacer SP is an insulator provided on a side surface of the contact LI. The contact LI is sandwiched between the spacers SP. The spacer SP separates and insulates between the contact LI and conductors (for example, word lines WL0 to WL7 and select gate lines SGD and SGS) adjacent to the contact LI in the Y direction. The spacer SP is, for example, an oxide film.
(3: Cross-Sectional Structure of First Wafer W1)
The conductive layer 20 is provided, for example, on a light absorption layer 120. The insulating layer 30 is provided on the conductive layer 20. The conductive layer 21 and the insulating layer 31 are alternately provided on the insulating layer 30. The insulating layer 32 is provided on the conductive layer 22 that is the uppermost layer. The conductive layer 23 is provided on the insulating layer 32. The insulating layer 33 is provided on the conductive layer 23. The conductive layer 24 is provided on the insulating layer 33. The contact V0 is provided on the conductive layer 24. The conductive layer 25 is provided on the contact V0. The contact V1 is provided on the conductive layer 25. The conductive layer 26 is provided on the contact V1. The contact V0, the conductive layer 25, and the contact VI are covered with the insulating layer 34. The insulating layer 34 can include a plurality of insulating layers. The insulating layer 35 is provided on the insulating layer 34.
Each of the conductive layers 21, 22, and 23 is formed, for example, in a plate shape extending along an XY plane. The conductive layer 24 is formed, for example, in a line shape extending in the Y direction. The conductive layers 20, 21, and 23 are used as the source line SL, the select gate line SGS, and the select gate line SGD, respectively. A plurality of conductive layers 22 is used in order from the bottom as the word lines WL0 to WL7. A portion where the memory pillar MP intersects the conductive layer 21 functions as the select transistor ST2. A portion where the memory pillar MP intersects the conductive layer 22 functions as the memory cell transistor MT. A portion where the memory pillar MP intersects the conductive layer 23 functions as the select transistor ST1. The conductive layer 24 is used as the bit line BL. The conductive layers 24 and 25 are connected via the contact V0. The conductive layer 25 and the conductive layer 26 are connected via the contact V1. The conductive layer 26 corresponds to the bonding pad BP. The conductive layer 26 includes, for example, copper.
The slit SLT has a plate-like portion formed in a plate shape extending along an XZ plane and divides the insulating layers 30 to 32 and the conductive layers 21 to 23. A bottom portion of the slit SLT is in contact with the conductive layer 20. The contact LI in the slit SLT is electrically connected to the conductive layer 20. In addition, the spacer SP in the slit SLT separates and insulates between each of the conductive layers 21 to 23 and the contact LI.
Each memory pillar MP is provided while extending along a Z direction and penetrates the insulating layer 30 to 32 and the conductive layer 21 to 23. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator provided while extending along the Z direction. The semiconductor layer 41 covers the core member 40. The semiconductor layer 41 is in contact with the conductive layer 20 via a side surface of the memory pillar MP. The stacked film 42 covers a side surface of the semiconductor layer 41 except for a portion where the semiconductor layer 41 and the conductive layer 20 are in contact with each other. The contact CV is provided on the semiconductor layer 41. The semiconductor layer 41 and the conductive layer 24 are connected via the contact CV.
The core member 40 is provided, for example, in a central portion of the memory pillar MP. The semiconductor layer 41 surrounds a side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds a side surface of the tunnel insulating film 43. The block insulating film 45 surrounds a side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. The semiconductor layer 41 is used as a channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Each of the tunnel insulating film 43 and the block insulating film 45 includes, for example, a silicon oxide film. The insulating film 44 is used as the charge storage layer of the memory cell transistor MT and includes, for example, a silicon nitride film. As a result, each memory pillar MP functions as one NAND string NS.
The insulating layer 50 is provided on the second wafer W2. The insulating layer 50 covers a second semiconductor circuit provided on the second wafer W2. The insulating layer 50 can include a plurality of insulating layers. The insulating layer 51 is provided on the insulating layer 50. The insulating layer 51 is in contact with the insulating layer 35. A boundary portion between the insulating layers 51 and 35 corresponds to a bonding surface between the first wafer W1 and the second wafer W2. The insulating layer 51 is, for example, a silicon oxide film.
The conductive layer GC is provided on a gate insulating film on the first wafer W1. The conductive layer GC is used as a gate electrode of the transistor. The contact C0 is provided on the conductive layer GC. Two contacts CS are connected to two impurity diffusion regions (not illustrated) corresponding to a source end and a drain end of the transistor. The conductive layers 52 are individually provided on the contacts CS and C0. The conductive layer 53 is provided on the conductive layer 52 via the contact C1. The conductive layer 54 is provided on the conductive layer 53 via the contact C2. The conductive layer 55 is provided on the conductive layer 54 via the contact C3. The conductive layer 55 corresponds to the bonding pad BP. The conductive layer 55 includes, for example, copper. The conductive layer 26 disposed so as to face the conductive layer 55 is in contact on the conductive layer 55. As a result, the conductive layer 24 (bit line BL) is electrically connected to the transistor provided on the first wafer W1.
The insulating layer 60 is provided on the conductive layer 20 (source line SL). Although not illustrated, the interconnect layer 400 includes a conductive layer connected to a semiconductor circuit included in either of the circuit layers 200 and 300. The conductive layer is connected to, for example, a pad PD provided while penetrating the insulating layer 60 (not illustrated). An interconnect connected via the bonding pad BP may be an interconnect other than the bit line BL.
The methods for manufacturing the semiconductor device 1 described in the first to third embodiments can also be used for the semiconductor device 1a as described in the fourth embodiment. Furthermore, in the fourth embodiment, a fluctuation range of a light absorption rate is suppressed by an antireflection layer 110 or 110a, whereby it is possible to suppress application of excessive heat to the circuit layer 200 at the time of laser peeling. As a result, a method of manufacturing the semiconductor device 1a according to the fourth embodiment can achieve effects similar to the effects of the first embodiment and can suppress property degradation of the memory cell transistor MT and the like due to the memory cell array 10 being heated.
A fifth embodiment relates to a method of manufacturing a semiconductor device 1 that suppresses fluctuations in a light absorption rate by irradiating a back surface of a first wafer W1 with laser beams having a plurality of wavelengths simultaneously. The following describes the details of the fifth embodiment, while referring mainly to differences from the first to fourth embodiments.
The following describes the method of manufacturing the semiconductor device 1 according to the fifth embodiment.
For example, a structure in which laser beams having two wavelengths are emitted along the same axis simultaneously includes a mirror M1 and a dichroic mirror M2. The mirror M1 reflects a laser beam. The dichroic mirror M2 reflects a light beam emitted on a front surface and transmits a light beam emitted on a back surface. In addition, the CO2 laser L1 is reflected by the mirror M1, passes through the dichroic mirror M2 and is emitted on the back surface of the first wafer W1. The CO2 laser L2 is reflected by the dichroic mirror M2 and emitted on the back surface of the first wafer W1. As a result, the CO2 lasers L1 and L2 are emitted on the back surface of the first wafer W1 along the same axis simultaneously. Then, the silicon oxide film OX generates heat by absorbing laser beams L1 and L2, and a vicinity of a portion in contact with a peeling surface of the first wafer W1 is plastically deformed based on the heat generated in the silicon oxide film OX. After that, the first wafer W1 is peeled with the silicon oxide film OX as a starting point, as in the first embodiment.
As described above, in a case where the peeling layer 100 (for example, silicon oxide film OX) is caused to absorb a CO2 laser having a wavelength of 9.3 μm in a process of peeling the first wafer W1, an interference effect of a light beam changes according to the thickness of a silicon substrate through which the laser beam passes. Specifically, a light absorption rate of the silicon oxide film OX may fluctuate by about 26%.
In contrast to this, the method of manufacturing the semiconductor device 1 according to the fifth embodiment uses the fact that a period of fluctuations in reflectance due to thin-film interference differs according to a wavelength, and a period of fluctuations in the light absorption rate, which is caused as a result of the difference of the period of fluctuations in the reflectance according to a wavelength, also differs according to a wavelength. Specifically, in the method of manufacturing the semiconductor device 1 according to the fifth embodiment, laser beams having a plurality of wavelengths such that influence caused by a change in the thickness of the silicon substrate is canceled are emitted along the same axis simultaneously, and effects of fluctuations are averaged. For example, in the case of a combination of wavelengths of 9.3 μm and 9.7 μm, periods of change are out of synchronization such that a crest and a trough cancel each other out. Therefore, it is possible to cancel the respective fluctuations in reflectance. As a result, with the combination of wavelengths of 9.3 μm and 9.7 μm, it is possible to reduce the final fluctuation ratio of light absorption to about 13%.
As described above, the method of manufacturing the semiconductor device 1 according to the fifth embodiment can more suppress fluctuations in the light absorption rate based on fluctuations in the wafer thickness by using laser beams having a plurality of wavelength in a peeling process of the first wafer W1 using laser peeling as compared with a case where a laser beam having a single wavelength is used. In other words, the method of manufacturing the semiconductor device 1 according to the fifth embodiment can suppress fluctuations in energy absorbed by the peeling layer 100 in the laser peeling and achieve a stable peeling process. As a result, the method of manufacturing the semiconductor device 1 according to the fifth embodiment can improve a yield of a manufacturing process of a semiconductor device that reuses the first wafer W1, and the method can suppress a manufacturing cost of the semiconductor device.
(14) 9.4+9.6, 0.179087, 0.299913
(15) 9.2+9.9, 0.17975, 0.262759
(16) 9.3+9.8, 0.180402, 0.239816
(17) 9.2+9.3, 0.185246, 0.211399
(18) 9.4+9.7, 0.188642, 0.389301
(19) 9.4+9.9, 0.194503, 0.317179
(20) 9.5+9.6, 0.203684, 0.271806
(21) 9.1+9.3, 0.203739, 0.249102
(22) 9.5+9.8, 0.207664, 0.263207
(25) 9.4+9.8, 0.229015, 0.291314
(26) 9.3+9.6, 0.229228, 0.248415
(27) 9.1+9.5, 0.247946, 0.272493
(23) 9.8+9.9, 0.207726, 0.291176
(24) 9.7+9.8, 0.211207, 0.363297
(28) 9.7+9.9, 0.24878, 0.389163
(29) 9.3+9.4, 0.258013, 0.265819
(30) 9.3+9.5, 0.27935, 0.237712
(31) 9.1+9.4, 0.284273, 0.3006
(32) 9.4+9.5, 0.2899, 0.28921
(33) 9.1+9.8, 0.31097, 0.274596
(34) 9.1+9.7, 0.327811, 0.372583
(35) 9.1+9.9, 0.331581, 0.300462
(36) 9.2+9.6, 0.343438, 0.245492
As described above, in a case where laser beams having a plurality of wavelengths are selected from the oscillation wavelength range of the CO2 laser, a combination in a wide range of 9.2 to 10 μm is effective. For example, in (1) to (29) in
A combination of laser beams having a plurality of wavelengths, which is good in terms of both the fluctuation range of the light absorption rate and the average light absorption rate, preferably includes laser beams having any wavelengths in a range of 9.7 to 9.9 μm and more preferably includes a laser beam having a wavelength of 9.7 μm. Specifically, as laser beams having a plurality of wavelengths, a first laser beam having any wavelength in a range of 9.7 to 9.9 μm is combined with a second laser beam having a wavelength that is a wavelength in a range of 9.2 to 9.9 μm and that is different from the wavelength of the first laser beam. In addition, in a case where a laser beam having a wavelength of 9.6 μm is selected, the laser beam is preferably combined with a laser beam having a wavelength that is any wavelength in a range of 9.3 to 9.9 μm and that is different from the wavelength of 9.6 μm. The method of manufacturing the semiconductor device 1 according to the fifth embodiment can suppress fluctuations in the light absorption rate and increase the average light absorption rate by using a combination of appropriate wavelengths as illustrated in
Note that the numerical values for the wavelengths exemplified in the present specification are not limited to numerical values that completely match the numerical values exemplified in the present specification. For example, in a case where there is a numerical value at the second decimal place in a numerical value of a wavelength, it suffices that a numerical value obtained by rounding off the numerical value at the second decimal place to the first decimal place corresponds to the value illustrated above.
The following describes modifications of the fifth embodiment.
The method of manufacturing the semiconductor device 1 according to the fifth embodiment may be combined with any of the first to third embodiments. In other words, in any of the first to third embodiments, laser beams having a plurality of wavelength may be emitted to a back surface of a first wafer W1 along the same axis simultaneously. Even in such as case, fluctuations in a light absorption rate can be suppressed as in the fifth embodiment.
Each embodiment described above can be variously modified.
In the above embodiments, each of the circuit configurations, the planar layouts, and the cross-sectional structures of the semiconductor devices 1 and 1a can be appropriately changed. For example, a semiconductor layer 41 of a memory pillar MP and a source line SL may be connected via a bottom of a memory pillar MP. The memory pillar MP may have a structure in which two or more pillars are connected in a Z direction. The memory pillar MP may have a structure in which a pillar corresponding to a select gate line SGD and a pillar corresponding to a word line WL are connected. Each contact may be connected by a plurality of contacts connected in the Z direction. A conductive layer may be inserted into a connecting portion of the plurality of contacts. The number of interconnect layers and the number of contacts included in the semiconductor device 1a can be appropriately changed.
In the present specification, “connection” means being electrically connected and does not exclude, for example, being electrically connected via another element in the middle. “Being electrically connected” may be done via an insulator as long as things electrically connected via the insulator can operate in a manner similar to things electrically connected. “Columnar” means being a structure provided in a hole formed in a manufacturing process of the semiconductor device 1. A “width” means, for example, a width of a constituent element in an X direction or a Y direction. A “wafer” or “semiconductor substrate” may be referred to as a “substrate”. A “semiconductor layer” may be referred to as a “conductive layer”. A “region” may be regarded as being in a configuration in which the region is included by a substrate used as a reference. A “planar position” means a position of the constituent element in a planar layout. A “top (plan) view” corresponds to, for example, viewing an object from a front side of the wafer. In the present specification, as a reference for measuring a pitch, an end of a pattern in the X direction or the Y direction may be used, or a central portion of a pattern may be used. Materials used for antireflection layers 110 and 110a, a light absorption layer 120, and the like can include impurities. It suffices that these layers use the silicon oxide film, the polysilicon, and the like described in the above embodiments as main materials.
While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-031384 | Mar 2023 | JP | national |
