between electrically conductive surfaces

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H01L2224/80895

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/80895between electrically conductive surfaces

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Capacitive coupling in a direct-bonded interface for microelectroni...
- Patent number 12,272,673
- Issue date Apr 8, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking structure, package structure and method of fabricating the...
- Patent number 12,272,674
- Issue date Apr 8, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and manufacturing method of the same
- Patent number 12,272,686
- Issue date Apr 8, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Fu-Jier Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D stacked chip that shares power rails
- Patent number 12,272,647
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Byounghak Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices having vertical transistors and stacked storage unit...
- Patent number 12,274,049
- Issue date Apr 8, 2025
- Yangtze Memory Technologies Co., Ltd.
- Dongxue Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory peripheral circuit having three-dimensional transistors and...
- Patent number 12,274,066
- Issue date Apr 8, 2025
- Yangtze Memory Technologies Co., Ltd.
- Chao Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated semiconductor packaging system with enhanced dielectric-...
- Patent number 12,272,670
- Issue date Apr 8, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jen-Yuan Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor structure having hybrid bondi...
- Patent number 12,266,622
- Issue date Apr 1, 2025
- NANYA TECHNOLOGY CORPORATION
- Yi-Jen Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically mounted die groups
- Patent number 12,266,634
- Issue date Apr 1, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jen-Yuan Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing substrate layered body and layered body
- Patent number 12,261,143
- Issue date Mar 25, 2025
- Mitsui Chemicals, Inc.
- Yasuhisa Kayaba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages
- Patent number 12,261,151
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chia-Hao Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optoelectronic device manufacturing method
- Patent number 12,261,161
- Issue date Mar 25, 2025
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- François Templier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method of semiconductor structure
- Patent number 12,261,149
- Issue date Mar 25, 2025
- Powerchip Semiconductor Manufacturing Corporation
- Shih-Ping Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded dies in semiconductor packages and methods of forming same
- Patent number 12,261,163
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jie Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrate rinse module in hybrid bonding platform
- Patent number 12,255,062
- Issue date Mar 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xin-Hua Huang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bond pads for semiconductor die assemblies and associated methods a...
- Patent number 12,255,163
- Issue date Mar 18, 2025
- Micron Technology, Inc.
- Bharat Bhushan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mirror image of geometrical patterns in stacked integrated circuit...
- Patent number 12,255,178
- Issue date Mar 18, 2025
- Mellanox Technologies, Ltd.
- Ido Bourstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming three-dimensional memory devices
- Patent number 12,255,181
- Issue date Mar 18, 2025
- Yangtze Memory Technologies Co., Ltd.
- Kun Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bonding system and method of using the same
- Patent number 12,255,171
- Issue date Mar 18, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Han-De Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices including substrates bonded to each other and...
- Patent number 12,255,126
- Issue date Mar 18, 2025
- SK hynix Inc.
- Mi Seon Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D semiconductor memory devices and structures
- Patent number 12,250,830
- Issue date Mar 11, 2025
- Monolithic 3D Inc.
- Zvi Or-Bach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated structure with bifunctional routing and assembly compris...
- Patent number 12,249,572
- Issue date Mar 11, 2025
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Candice Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged device including an optical path structure aligned to an o...
- Patent number 12,248,178
- Issue date Mar 11, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset pads over TSV
- Patent number 12,243,851
- Issue date Mar 4, 2025
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Bongsub Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method for manufacturing the same
- Patent number 12,237,283
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically mounted die groups
- Patent number 12,237,303
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jen-Yuan Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor device with redistribution str...
- Patent number 12,237,318
- Issue date Feb 25, 2025
- NANYA TECHNOLOGY CORPORATION
- Tse-Yao Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 12,237,239
- Issue date Feb 25, 2025
- Amkor Technology Singapore Holding Pte Ltd.
- Jin Young Khim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package and method of manufacture
- Patent number 12,237,288
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuan-Yu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shield structure for backside through substrate vias (TSVs)
- Patent number 12,230,554
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Min-Feng Kao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITE...
- Publication number 20250118693
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Bharat Bhushan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE WITH MULTIPLE HBM STACKS
- Publication number 20250118719
- Publication date Apr 10, 2025
- ADVANCED MICRO DEVICES, INC.
- Brett P. WILKERSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Mitigating process problems in hybrid bonding of vertical die stacking
- Publication number 20250118692
- Publication date Apr 10, 2025
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
- Publication number 20250118710
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuo-Ming WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Semiconductor Package and Semiconductor Package
- Publication number 20250118649
- Publication date Apr 10, 2025
- Yibu Semiconductor Co., Ltd.
- Weiping LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHODS FOR A MULTI-STACK ARCHITECTURE
- Publication number 20250118677
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Jin YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SPLIT SUPPORT PILLAR STR...
- Publication number 20250113484
- Publication date Apr 3, 2025
- WESTERN DIGITAL TECHNOLOGIES, INC.,
- Masato NOGUCHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES
- Publication number 20250112199
- Publication date Apr 3, 2025
- Intel Corporation
- Thomas Sounart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...
- Publication number 20250112200
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...
- Publication number 20250112077
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES
- Publication number 20250112173
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PHOSPHORUS-DOPED SILICON...
- Publication number 20250113486
- Publication date Apr 3, 2025
- WESTERN DIGITAL TECHNOLOGIES, INC.,
- Nobuyuki FUJIMURA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY UNDULATING ISO...
- Publication number 20250113492
- Publication date Apr 3, 2025
- WESTERN DIGITAL TECHNOLOGIES, INC.,
- Wataru MURANAGA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE AND METHOD
- Publication number 20250112137
- Publication date Apr 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shih-Wei Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUANTUM DOT IMAGE SENSOR DEVICES AND METHODS OF MANUFACTURING THE SAME
- Publication number 20250113700
- Publication date Apr 3, 2025
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Rajesh KATKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT
- Publication number 20250112187
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRAME STRUCTURES IN SEMICONDUCTOR PACKAGES
- Publication number 20250112176
- Publication date Apr 3, 2025
- Apple Inc.
- Jiongxin LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY UNDULATING ISO...
- Publication number 20250113485
- Publication date Apr 3, 2025
- Western Digital Technologies, Inc.
- Wataru MURANAGA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGHLY PROTECTIVE WAFER EDGE SIDEWALLl PROTECTION LAYER
- Publication number 20250112102
- Publication date Apr 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Su-Jen Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE
- Publication number 20250112186
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20250107109
- Publication date Mar 27, 2025
- Seoul National University R&DB Foundation
- Cheol Seong Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTU...
- Publication number 20250105181
- Publication date Mar 27, 2025
- Samsung Electronics Co., Ltd.
- Jumyong PARK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAMINATE MANUFACTURING METHOD AND LAMINATE
- Publication number 20250105205
- Publication date Mar 27, 2025
- Resonac Corporation
- Yuki IMAZU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE
- Publication number 20250104761
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGES WITH DOUBLE HYBRID BONDED DIES AND METH...
- Publication number 20250105207
- Publication date Mar 27, 2025
- Intel Corporation
- Omkar Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D Multichip Package
- Publication number 20250105238
- Publication date Mar 27, 2025
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE INCLUDING STRESS-REDUCTION CHAMFERS AND METHO...
- Publication number 20250105170
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Tsung-Yen Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method
- Publication number 20250105172
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Chiang Ting
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OVERSIZED VIA AS THROUGH-SUBSTRATE-VIA (TSV) STOP LAYER
- Publication number 20250105098
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Feng Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE LAYER TRANSFER
- Publication number 20250105046
- Publication date Mar 27, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS

between electrically conductive surfaces

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Capacitive coupling in a direct-bonded interface for microelectroni...

Stacking structure, package structure and method of fabricating the...

Semiconductor structure and manufacturing method of the same

3D stacked chip that shares power rails

Memory devices having vertical transistors and stacked storage unit...

Memory peripheral circuit having three-dimensional transistors and...

Integrated semiconductor packaging system with enhanced dielectric-...

Method of manufacturing semiconductor structure having hybrid bondi...

Vertically mounted die groups

Method of manufacturing substrate layered body and layered body

Integrated circuit packages

Optoelectronic device manufacturing method

Manufacturing method of semiconductor structure

Molded dies in semiconductor packages and methods of forming same

Integrate rinse module in hybrid bonding platform

Bond pads for semiconductor die assemblies and associated methods a...

Mirror image of geometrical patterns in stacked integrated circuit...

Methods for forming three-dimensional memory devices

Wafer bonding system and method of using the same

Semiconductor devices including substrates bonded to each other and...

3D semiconductor memory devices and structures

Integrated structure with bifunctional routing and assembly compris...

Packaged device including an optical path structure aligned to an o...

Offset pads over TSV

Semiconductor structure and method for manufacturing the same

Vertically mounted die groups

Method for fabricating semiconductor device with redistribution str...

Semiconductor device and manufacturing method thereof

Semiconductor die package and method of manufacture

Shield structure for backside through substrate vias (TSVs)

Patents Applicationslast 30 patents

TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITE...

CHIP PACKAGE WITH MULTIPLE HBM STACKS

Mitigating process problems in hybrid bonding of vertical die stacking

SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

Method for Forming Semiconductor Package and Semiconductor Package

SYSTEM AND METHODS FOR A MULTI-STACK ARCHITECTURE

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SPLIT SUPPORT PILLAR STR...

SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES

HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...

ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...

PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PHOSPHORUS-DOPED SILICON...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY UNDULATING ISO...

INTEGRATED CIRCUIT PACKAGE AND METHOD

QUANTUM DOT IMAGE SENSOR DEVICES AND METHODS OF MANUFACTURING THE SAME

IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT

FRAME STRUCTURES IN SEMICONDUCTOR PACKAGES

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY UNDULATING ISO...

HIGHLY PROTECTIVE WAFER EDGE SIDEWALLl PROTECTION LAYER

TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTU...

LAMINATE MANUFACTURING METHOD AND LAMINATE

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE

INTEGRATED CIRCUIT PACKAGES WITH DOUBLE HYBRID BONDED DIES AND METH...

3D Multichip Package

SEMICONDUCTOR PACKAGE INCLUDING STRESS-REDUCTION CHAMFERS AND METHO...

Semiconductor Device and Method

OVERSIZED VIA AS THROUGH-SUBSTRATE-VIA (TSV) STOP LAYER

SELECTIVE LAYER TRANSFER