Claims
- 1. A method of manufacturing a semiconductor memory, comprising:forming a capacitor structure by growing a high ferroelectric oxide thin film as a capacitor insulating film between a lower electrode and an upper electrode; and forming an integrated capacitor by growing a protective film covering said capacitor structure, wherein the method further comprises forming an oxygen-containing layer between a boundary of said upper electrode and said high ferroelectric oxide thin film in a region near to a surface of said high ferroelectric oxide thin film, and not in a region of said upper electrode, by introducing oxygen into the upper electrode/high ferroelectric oxide thin film boundary through said upper electrode, after forming said protective film by plasma treatment.
- 2. A method of manufacturing a semiconductor memory according to claim 1, wherein said forming said oxygen-containing layer between said boundary of said upper electrode and high ferroelectric oxide thin film through said upper electrode, is an annealing step in an oxygen atmosphere.
- 3. A method of manufacturing a semiconductor memory according to claim 2, wherein said growing said protective film covering said capacitor structure is a silicon hydride or a tetraethoxysilane plasma-assisted decomposition step.
- 4. A method of manufacturing a semiconductor memory according to claim 3, wherein said annealing step in an oxygen atmosphere is a step wherein annealing is performed at a temperature of 400-575° C. at atmospheric pressure for at least 10 minutes.
- 5. A method of manufacturing a semiconductor memory, comprising:forming a capacitor structure by growing a high ferroelectric oxide thin film as a capacitor insulating film between a lower electrode and an upper electrode; and forming an integrated capacitor by growing a protective film covering said capacitor structure by plasma treatment, wherein the method further comprises forming a oxygen-containing layer between a boundary of said upper electrode and said high ferroelectric oxide thin film in a region near to a surface of said high ferroelectric oxide thin film and not in a region of said upper electrode, by introducing oxygen into the upper electrode/high ferroelectric oxide thin film boundary through said upper electrode after forming said upper electrode in the steps for forming said capacitor structure.
- 6. A method of manufacturing a semiconductor memory according to claim 5, wherein said forming said oxygen-containing layer between said boundary of said upper electrode and said high ferroelectric oxide thin film through said upper electrode, is an annealing step in an oxygen atmosphere.
- 7. A method of manufacturing a semiconductor memory according to claim 6, wherein said annealing step in an oxygen atmosphere is a step wherein annealing is performed at a temperature of 400-575° C. at atmospheric pressure for at least 10 minutes.
- 8. A method of manufacturing a semiconductor memory according to claim 5, wherein said growing said protective film covering said capacitor structure is a silicon hydride or a tetraethoxysilane plasma-assisted decomposition step.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 8-178907 |
Jul 1996 |
JP |
|
Parent Case Info
This application is a Divisional application of application Ser. No. 09/214,382, U.S. Pat. No. 6,309,894 filed Jan. 6, 1999, which is a national stage application filed under 35 USC 371 of International application No. PCT/JP97/02322, filed Jul. 4, 1997.
US Referenced Citations (2)
| Number |
Name |
Date |
Kind |
|
5568352 |
Hwang |
Oct 1996 |
A |
|
5909043 |
Summerfelt |
Jun 1999 |
A |
Foreign Referenced Citations (3)
| Number |
Date |
Country |
| 6-1365 |
Jan 1994 |
JP |
| 7-263570 |
Oct 1995 |
JP |
| 8-55967 |
Feb 1996 |
JP |
Non-Patent Literature Citations (4)
| Entry |
| K. Koyama, et al., “A Stacked Capacitor with (BaxSr 1−x)TiO2for 256M DRAM”, IEEE Int'l Electron Device Meeting, pp. 823-826 (1991).* |
| N. Tanabe, et al., “A Ferroelectric Capacitor over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories”, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 123-124.* |
| Hase, et al., “Analysis of the Degradation of PT and SrBi2 Ta2 O9 Thin Films with a Reductive Process”, 8th Int'Symposium on Integrated Ferroelectrics, 11c(1996).* |
| Maniar, et al., “Impact of Backend Processing on Integrated Feroelectrics Capacitor Characteristics”, Material Research Society Symposium Proceedings, vol. 310, pp. 151-156 (1993). |