Patent Application
20230290874
The present disclosure relates to a method of manufacturing a silicon carbide semiconductor device having trench gates and a method of manufacturing a power conversion apparatus including the silicon carbide semiconductor device.
A power semiconductor device in which unipolar switching elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistor) and unipolar freewheeling diodes such as Schottky Barrier Diode (SBD) are built-in, has been known. Such a semiconductor device can be realized by arranging MOSFET cells and SBD cells in parallel on the same chip, and typically be realized by providing a Schottky electrode in a specific region within the chip and operating that region as an SBD.
By having the freewheeling diode built-in in the chip of the switching element, the cost can be reduced compared to the case where the freewheeling diode is externally attached to the switching element. In particular, in a MOSFET using silicon carbide (SiC) as a base material, suppression of bipolar operation due to the parasitic pn diode by having the SBD built-in thereof is one of the benefits. This is because, in a silicon carbide semiconductor device, the reliability of the device may be impaired due to the expansion of crystal defects caused by recombination energy of carriers due to parasitic pn diode operation.
Also, in comparison with a planar type MOSFET having a structure in which the gate electrode is formed on the surface of the semiconductor layer, in a trench gate type MOSFET having a structure in which a gate electrode is embedded in a trench formed in a semiconductor layer, a channel can be formed on the sidewall of the trench, which improves the channel width density, reducing the on-resistance.
When manufacturing such a trench type MOSFET with built-in SBD, a Schottky trench in which the Schottky electrode is embedded and a gate trench in which the gate electrode is embedded are formed by an etching method, a gate insulating film and a gate electrode are formed in the gate trench, an interlayer insulating film is formed thereon, a contact hole is formed in the interlayer insulating film, and, concurrently, an Ni film is deposited and heat-treated to form a silicide layer, while leaving part of the interlayer insulating film on the sidewall of the Schottky trench (for example, Patent Document 1).
[Patent Document 1] Japanese Patent Application Laid-Open No. 2018-182235 (
Accordingly, in the case in which the Schottky trench is formed and then, polycrystalline silicon, which is to be the gate electrode, is formed in the gate trench, and silicide such as metal silicide is formed on the source region in the state where the Schottky trench is filled with the interlayer insulating film, polycrystalline silicon and Ni remain in the holes (cavities, cracks) formed in the interlayer insulating film filled in the Schottky trench, polycrystalline silicon, metal and its silicide remain where they should not exist, and they are released as foreign matters when the interlayer insulating film is removed, causing contamination in some cases.
Also, when forming a gate insulating film of silicon oxide and a gate electrode of polycrystalline silicon in a gate trench, the polycrystalline silicon is processed by a dry etching method in many cases, when silicon oxide and polycrystalline silicon are also once formed in the Schottky trench in the same manner as the gate trench, and the polycrystalline silicon in the Schottky trench is removed by dry etching, part of the polycrystalline silicon may remain on the gate insulating film at the bottom of the Schottky trench, if silicidation is performed by depositing and heating a metal layer in this state, silicide may be formed also at the bottom of the Schottky trench, the silicide is released in a later step, causing contamination in some cases.
The present disclosure has been made to solve the above-described problems, and an object thereof is to provide a method of manufacturing a silicon carbide semiconductor device in which polycrystalline silicon material or metal silicide material remaining in unintended parts is prevented with little defective or high reliability.
According to the present disclosure, a method of manufacturing a silicon carbide semiconductor device includes a step of forming a drift layer of a first conductive type on a silicon carbide semiconductor substrate, a step of forming a well region of a second conductive type on the drift layer, forming a source region of the first conductive type in an upper layer portion of the well region, a step of forming a gate trench extending through the source region and the well region and reaching the drift layer, a step of forming a Schottky trench provided apart from the gate trench and reaching the drift layer, a step of forming a silicon oxide film in contact with the inner walls of the gate trench and the Schottky trench, a step of forming a polycrystalline silicon film inside the silicon oxide film in the gate trench and the Schottky trench, a step of forming a gate electrode in the gate trench by removing the polycrystalline silicon film outside the gate trench and the Schottky trench by etching back the polycrystalline silicon film, a step of forming an interlayer insulating film on the gate electrode in the gate trench, a step of removing, by wet etching, the polycrystalline silicon film in the Schottky trench after opening a hole in the interlayer insulating film, after the step of removing the polycrystalline silicon film in the Schottky trench, a step of forming an ohmic electrode on the source region, after the step of forming the ohmic electrode, a step of removing the silicon oxide film inside the Schottky trench, and after the step of removing the silicon oxide film in the Schottky trench, a step of forming a source electrode to be in a Schottky junction with the drift layer in the Schottky trench.
According to the present disclosure, the method of manufacturing the silicon carbide semiconductor device ensures to manufacture the silicon carbide semiconductor device with little defective or high reliability.
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Hereinafter, embodiments will be described with reference to the attached drawings. It should be noted that the drawings are illustrated schematically, and the mutual relationship between the sizes and positions of the images illustrated in different drawings is not necessarily accurately illustrated and may be changed as appropriate. In addition, in the following description, the same components are denoted and illustrated by the same reference numerals, and the names and functions thereof are also similar. Accordingly, detailed descriptions thereof may be omitted.
First, the structure of a silicon carbide semiconductor device manufactured by a method of manufacturing according to a first embodiment of the present disclosure will be described.
In
Gate trenches extending through the source regions 40 and the well region 30 and reaching the drift layer 20 are formed at portions in the well region 30 where the source regions 40 are formed. Schottky trenches extending through the well region 30 and reaching the drift layer 20 are formed at portions each apart from the gate trenches in the well region 30 where the source regions 40 are not formed.
Inside the gate trench, a gate electrode 60 composed of low-resistance polycrystalline silicon is formed via a gate insulating film 50. A first protection region 31 of p-type is formed in the drift layer 20 at the bottom of the gate trench. A second protection region 32 of p-type is formed in the drift layer 20 at the bottom of the Schottky trench.
An interlayer insulating film 55 is formed on the gate electrodes 60 and the gate insulating film 50 in the gate trenches and in the vicinity of the openings of the Schottky trenches. Ohmic electrodes 70 composed of metal silicide are formed on the source regions 40 and the contact regions 35. A source electrode 80 is formed inside the Schottky trenches, on the ohmic electrodes 70, and on the interlayer insulating film 55, and the source electrode 80 inside the Schottky trench and the drift layer 20 are in Schottky junction. A rear surface ohmic electrode 71 and a drain electrode 85 are formed on the surface of the semiconductor substrate 10 opposite to the drift layer 20 where the drift layer 20 is not formed.
At a position where the source electrode 80 is in contact with the drift layer 20 in the Schottky trench, the source electrode 80 is composed of any materials of Ti, Mo, W, and Ni.
As illustrated in the plan view of
Hereafter, the method of manufacturing a SiC-MOSFET with built-in SBD being a silicon carbide semiconductor device according to the first embodiment of the present disclosure, will be described with reference to cross-sectional views of
On the semiconductor substrate 10 composed of n-type low-resistance silicon carbide having a (0001) plane orientation of the first main surface with an off angle and a 4H polytype, the drift layer 20 composed of silicon carbide is epitaxially grown with an impurity concentration of 1×1015 cm-3 or more and 1×1017 cm-3 or less and a thickness of 5 µm or more and 50 µm or less by chemical vapor deposition (CVD method).
Subsequently, Al (aluminum), which is a p-type impurity, is ion-implanted into the front surface of the drift layer 20. At this point, the depth of ion implantation of Al is about 0.5 to 3 µm, which does not exceed the thickness of the drift layer 20. The impurity concentration of ion-implanted Al is in the range of 1×1017 cm-3 or more and 1×1019 cm-3 or less, which is higher than the impurity concentration of the drift layer 20. The region implanted with Al ions in the step becomes the well region 30, and the structure illustrated in the cross section in
Next, an implantation mask is formed with a photoresist or the like so that predetermined portions of the well region 30 on the front surface of the drift layer 20 are opened, and N (nitrogen), which is an n-type impurity, is ion-implanted. The ion implantation depth of N is assumed to be shallower than the thickness of the well region 30. The impurity concentration of ion-implanted N is in the range of 1×1018 cm-3 or more and 1×1021 cm-3 or less and exceeds the p-type impurity concentration of the well region 30. Of the regions into which N is implanted in the step, the regions exhibiting the n-type become the source regions 40. After this, the implantation mask is removed.
Further, with the same method, into predetermined regions of the well region 30 adjacent to the source regions 40, Al is ion-implanted with an impurity concentration in the range of 1×1019 cm-3 or more and 1×1021 cm-3 or less, which is higher than the impurity concentration of the well region 30, thereby forming the contact regions 35. Up until this step, the structure of the cross-sectional view illustrated in
Next, a resist mask is formed to partially open regions where the source regions 40 are formed, and the gate trenches each of which extends through the source region 40 and the well region 30 and reaches the drift layer 20 are formed by dry etching. Similarly, a resist mask is formed to partially open regions where the source regions 40 are not formed, and the Schottky trenches each of which extends through the well region 30 and reaches the drift layer 20 are formed by dry etching.
The gate trenches and the Schottky trenches may be formed with the same depth in the same dry etching process. Up until this step, the structure of the cross-sectional view illustrated in
Subsequently, as illustrated in the schematic cross-sectional view of
Next, annealing is performed in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour using a heat treatment apparatus. The annealing electrically activates the ion-implanted N and Al.
Subsequently, the silicon carbide layer front surface including inside the gate trenches and the Schottky trenches is thermally oxidized to form a silicon oxide film 51 having a thickness of 10 nm or more and 300 nm or less. The silicon oxide film 51 is formed in contact with the inner walls of the gate trenches and the Schottky trenches. The silicon oxide film 51 may be formed by the CVD method. Up until this step, the structure of the cross-sectional view illustrated in
Next, a polycrystalline silicon film 61 having conductivity and a thickness of 300 nm or more and 2000 nm or less is formed on the silicon oxide film 51 by the low-pressure CVD method, thereby forming the one in the cross-sectional view illustrated in
Subsequently, as illustrated in a schematic cross-sectional view of
Next, the interlayer insulating film 55 and the silicon oxide film 51 are patterned so as to open above the regions where the source regions 40 and the contact regions 35 are formed and above the Schottky trenches to form the cross-sectional structure illustrated in
Subsequently, as illustrated in the cross-sectional view of
Next, ohmic electrodes 70 composed of silicide are formed on the source regions 40 and the contact regions 35, as illustrated in the cross-sectional view of
Subsequently, as illustrated in the cross-sectional view of
Next, a source electrode 80 to be in a Schottky junction with the drift layer 20 is formed inside the Schottky trenches and on the ohmic electrodes 70 of the gate trenches, and by forming the back surface ohmic electrode 71 and the drain electrode 85 on the rear surface side, the SiC-MOSFET with built-in SBD whose cross section is illustrated in
As in one of the conventional methods, when forming a contact hole in the interlayer insulating film 55 that leads to the ohmic electrodes 70 with the Schottky trenches filled with the interlayer insulating film 55, it was necessary to form a contact hole while covering the Schottky trenches with a resist mask, and then form another resist mask to remove the interlayer insulating film 55 in the Schottky trenches. However, manufacturing the SiC-MOSFET with built-in SBD by the method of manufacturing of the present embodiment allows manufacturing the SiC-MOSFET with built-in SBD with the number of times of forming resist masks reduced, reducing the manufacturing cost.
When the SiC-MOSFET with built-in SBD is manufactured by the method of manufacturing of the present embodiment, the silicon oxide film 51 and parts (surface) of the interlayer insulating film 55 are wet-etched when the silicon oxide film 51 in the inside the Schottky trenches is wet-etched; therefore, portions have emerged where the source electrode 80 and the source region 40 or the contact region 35 are in direct contact with each other on the gate trench side around the ohmic electrode 70, as illustrated in the cross-sectional view of
According to the method of manufacturing the silicon carbide semiconductor device of the present embodiment, remaining of the silicide and the gate insulating film in the Schottky trenches is prevented, and adding foreign matter, which causes contamination during steps, is also prevented; therefore, a silicon carbide semiconductor device with few defects can be manufactured.
First, the structure of a silicon carbide semiconductor device manufactured by a method of manufacturing according to a second embodiment of the present disclosure will be described.
In the first embodiment, the ohmic electrodes 70 of the MOSFET in the gate trenches have been formed in the holes formed in the positions separated from the holes in the interlayer insulating film 55 in the upper parts of the Schottky trenches in the cross-sectional view. However, in a method of manufacturing a silicon carbide semiconductor device according to the present embodiment, the ohmic electrodes 70 of the MOSFET in the gate trenches and the source electrode 80 inside the Schottky trenches are formed in the same hole of the interlayer insulating film 55, that is, the interlayer insulating film 55 is not provided between the ohmic electrodes 70 and the Schottky trenches 55 which are adjacent to each other. The other respects are the same as those of the first embodiment; therefore, detailed description thereof will be omitted.
In
The gate insulating film 50 is formed the inside the gate trench, and the gate electrode 60 is formed inside thereof. A first protection region 31 of p-type is formed in the drift layer 20 at the bottom of the gate trench. A second protection region 32 is formed in the drift layer 20 at the bottom of the Schottky trench.
An interlayer insulating film 55 is formed on the gate electrodes 60 and the gate insulating film 50 in the gate trenches. Ohmic electrodes 70 are formed on the source regions 40, the contact regions 35, and the well regions 30 in the vicinity of the Schottky trenches. No interlayer insulating film 55 is formed between the ohmic electrodes 70 and the Schottky trenches which are adjacent to each other. Source electrode 80 is formed inside the Schottky trenches, on the ohmic electrodes 70, and on the interlayer insulating film 55, and the source electrode 80 inside the Schottky trench and the drift layer 20 are in Schottky junction. A rear surface ohmic electrode 71 and a drain electrode 85 are formed on the surface of the semiconductor substrate 10 opposite to the drift layer 20 where the drift layer 20 is not formed.
Further, in
Hereafter, the method of manufacturing a SiC-MOSFET with built-in SBD being a silicon carbide semiconductor device according to the second embodiment of the present disclosure, will be described with reference to cross-sectional views of
In the method of manufacturing the silicon carbide semiconductor device of the present embodiment, the Steps from
Subsequently, as illustrated in the cross-sectional view of
Next, through steps such as depositing and annealing the metal that composing the ohmic electrode 70, as illustrated in the cross-sectional view of
Subsequently, as illustrated in the cross-sectional view of
Next, a source electrode 80 to be in a Schottky junction with the drift layer 20 is formed on the interlayer insulating film 55 and the inside the Schottky trenches and on the ohmic electrodes 70 of the gate trenches, and by forming the back surface ohmic electrode 71 and the drain electrode 85 on the rear surface side, the SiC-MOSFET with built-in SBD whose cross section is illustrated in
Here, in some cases, the ohmic electrode 70 is formed from the outside of the opening of the Schottky trench to a part of the inside the Schottky trench, and as illustrated in the cross-sectional view of
Further, the silicon oxide film 51 and parts (surface) of the interlayer insulating film 55 are wet-etched when the silicon oxide film 51 in inside the Schottky trenches is wet-etched; therefore, portions have emerged where the source electrode 80 and the source region 40 or the contact region 35 are in direct contact with each other on the gate trench side around the ohmic electrode 70, as illustrated in the cross-sectional view of
According the method of manufacturing a SiC-MOSFET with built-in SBD being the silicon carbide semiconductor device according to the present embodiment, remaining of the silicide and the gate insulating film in the Schottky trenches is prevented, and adding foreign matter, which causes contamination during steps, is also prevented; therefore, a silicon carbide semiconductor device with few defects can be manufactured.
Further, according to the silicon carbide semiconductor device of the present embodiment, forming the interlayer insulating film 55 in the vicinity of the Schottky trench is not required and there is no need to secure a space for forming the interlayer insulating film 55, the distance between the trenches can be made smaller; therefore, the silicon carbide semiconductor device with a higher current density can be manufactured.
Although the method of forming the well regions 30 and the source regions 40 by ion implantation has been described in the first and second embodiments, the well regions 30 and the source regions 40 may be formed by another method, for example, they are formed by an epitaxial method. Moreover, although the example in which the well regions 30 are formed over the entire surface has been described, the well regions 30 may be formed in part of the upper layer portion of the drift layer 20. At that time, the Schottky trenches may be provided directly from the surface of the drift layer 20 instead of extending through the well regions 30.
Further, although in the first and second embodiments, the examples in which the first protection regions 31 and the second protection regions 32 are provided in the lower part of the trenches have been described, the first protection regions 31 and the second protections region 32 may not be provided in some cases. At this point, neither the first connection regions 33 nor the second connection regions 34 may be provided.
Furthermore, in the first and second embodiments, although aluminum (Al) is used as the p-type impurities, the p-type impurities may be boron (B) or gallium (Ga). The n-type impurities may be phosphorus (P) instead of nitrogen (N). In the MOSFETs described in the first and second embodiments, the gate insulating film is not necessarily an oxide film such as SiO2 and may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. Further, although in the above-described embodiments, the crystal structure, the plane orientation of the main surface, the off-angle, the implantation conditions, and the like have been described with specific examples, the scope of application is not limited to these numerical ranges.
Further, in the above-described embodiment, the configuration in which an SBD is built-in in a so-called vertical MOSFET silicon carbide semiconductor device in which the drain electrode 85 is formed on the rear surface of the semiconductor substrate 10. However, a configuration is also adoptable in which an SBD is built-in in a so-called lateral MOSFET such as a RESURF (REduced SURface Field) type MOSFET in which the drain electrode 85 is formed on the surface of the drift layer 20. Further, the silicon carbide semiconductor device may be an insulated gate bipolar transistor (IGBT) with a built-in SBD. It can also be adoptable to a MOSFET and an IGBT having a super junction structure with a built-in SBD.
In the present embodiment, the method of manufacturing the silicon carbide semiconductor device according to the above-described first and second embodiments is applied to a power conversion apparatus. Although the present disclosure is not limited to a method of manufacturing a specific power conversion apparatus, hereinafter, as a third embodiment, a case where the present disclosure is applied to a three-phase inverter will be described.
The power conversion system illustrated in
The power conversion apparatus 200 is a three-phase inverter connected between the power supply 100 and the load 300, which converts the DC power supplied from the power supply 100 into AC power and supplies AC power to the load 300. As illustrated in
The drive circuit 202 turns off each normally-off switching element by setting the voltage of the gate electrode and the voltage of the source electrode to the same potential.
The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion apparatus 200. The load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioning apparatus.
Hereinafter, the detailed description is made on the power conversion apparatus 200. The main conversion circuit 201 includes a switching element and a freewheeling diode (not illustrated), and by switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, and the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and six freewheeling diodes each of which is anti-parallel with the respective switching elements. For each switching element of the main conversion circuit 201, the silicon carbide semiconductor device manufactured by the method of manufacturing the silicon carbide semiconductor device according to any one of the first to third embodiments described above is applied. Each of the two switching elements connected in series among the six switching elements constitutes an upper and lower arm, and each upper and lower arm constitutes each phase (U-phase, V-phase, W-phase) of the full bridge circuit. Then, the output terminal of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
The drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in response to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) equal to or higher than a threshold voltage of the switching element, and when the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) equal to or lower than the threshold voltage of the switching element.
The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (ON time) for each switching element of the main conversion circuit 201 to be in the ON state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 is controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an ON signal is output to the switching element which is supposed to be turned on at each time point and an OFF signal is output to the switching element which is supposed to be turned off. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to the control signal.
In the power conversion apparatus according to the present embodiment, the application of the silicon carbide semiconductor device manufactured by the method of manufacturing the silicon carbide semiconductor device according to the first and second embodiments to a switching element of the main conversion circuit 201, ensures a power conversion apparatus with low loss and improved reliability in high-speed switching.
Although in the present embodiment, the example where the present disclosure is applied to the two-level three-phase inverter has been described, the present disclosure is not limited there to, and can be applied to various power conversion apparatuses. Although in the present embodiment, a two-level power conversion apparatus is adopted, a three-level or multi-level power conversion apparatus may also be adoptable, and when power is supplied to a single-phase load, the present disclosure may also be adopted to a single-phase inverter. Further, when supplying power to a DC load or the like, the present disclosure is adoptable to the DC/DC converter or the AC/DC converter.
Further, the power conversion apparatus to which the resent disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, the power conversion apparatus can be applied to the case where a load is a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a contactless power supply system, further applied to the case where a load is a power conditioner for a solar power generation system and a power storage systems, for example.
10 SiC substrate, 20 drift layer, 30 well region, 31 first protection region, 32 second protection region, 33 first connection region, 34 second connection region, 35 connection region, 40 source region, 50 gate insulating film, 51 silicon oxide film, 55 interlayer insulating film, 60 gate electrode, 61 polycrystalline silicon film, 70 ohmic electrode, 71 rear surface ohmic electrode, 80 source electrode, 85 drain electrode, 90 resist mask, 100 power supply, 200 power conversion apparatus, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/037178 | 9/30/2020 | WO |
