Claims
- 1. A process for forming a silicon layer over a semiconductor substrate, said process comprising:
forming a doped polysilicon layer over said semiconductor substrate; forming an oxide layer on said doped polysilicon layer having a substantially uniform thickness in a range from about 1 Angstrom to about 20 Angstroms; and forming an overlying silicon-containing layer upon said oxide layer, said oxide layer substantially preventing diffusion of dopants from said doped polysilicon layer into said overlying silicon-containing layer.
- 2. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of amorphous silicon.
- 3. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of polysilicon.
- 4. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of cylindrical grain silicon.
- 5. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of monocrystalline silicon.
- 6. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of hemispherical grain silicon.
- 7. A process as recited in claim 1, wherein said overlying silicon-containing layer is substantially composed of spherical grain silicon.
- 8. A process as recited in claim 1, wherein forming said oxide layer comprises exposing said doped polysilicon layer to an oxidizing bath.
- 9. A process as recited in claim 1, wherein forming said oxide layer comprises exposing said doped polysilicon layer to an oxidizing agent formed from ozone.
- 10. A process as recited in claim 1, wherein forming said oxide layer comprises exposing said doped polysilicon layer to an oxidizing agent formed from hydrogen peroxide.
- 11. A process as recited in claim 1, wherein forming said oxide layer comprises exposing said doped polysilicon layer to an oxidizing agent formed from diatomic oxygen.
- 12. A process as recited in claim 1, wherein forming said oxide layer comprises exposing said doped silicon layer to an aqueous solution containing an oxidizing agent in an oxidation process conducted at a temperature less than about 200° C.
- 13. A process as recited in claim 1, wherein said doped polysilicon layer is doped with phosphorous.
- 14. A process as recited in claim 1, wherein said doped polysilicon layer is doped with boron.
- 15. A process as recited in claim 1, wherein said doped polysilicon layer is doped with arsenic.
- 16. A process for forming a silicon layer over a semiconductor substrate, said process comprising:
forming a first layer over said semiconductor substrate, said first layer being substantially composed of a material selected from the group consisting of polysilicon, hemispherical grain silicon, spherical grain silicon, amorphous silicon, and monocrystalline silicon; forming an oxide layer upon said first layer having a thickness in a range from about 1 Angstrom to about 20 Angstroms; and forming a second layer upon said oxide layer, said second layer being substantially composed of a material selected from the group consisting of polysilicon, hemispherical grain silicon, spherical grain silicon, cylindrical grain polysilicon, amorphous silicon, and monocrystalline silicon.
- 17. A process as recited in claim 16, wherein said oxide layer has a thickness of from about one to about nine molecules of silicon dioxide.
- 18. A process as recited in claim 16, wherein said semiconductor substrate comprises silicon on sapphire.
- 19. A process as recited in claim 16, wherein said semiconductor substrate comprises silicon on insulator.
- 20. A process as recited in claim 16, wherein said semiconductor substrate comprises silicon on glass.
- 21. A process for forming a structure over a semiconductor substrate, said process comprising:
forming a first layer over said semiconductor substrate, said first layer being substantially composed of a material selected from the group consisting of polysilicon, hemispherical grain silicon, spherical grain silicon, amorphous silicon, and monocrystalline silicon; forming an oxide layer upon said first layer having a thickness in a range from about 1 Angstrom to about 20 Angstroms; and forming a second layer upon said oxide layer, said second layer being substantially composed of a material selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, cylindrical grain polysilicon, hemispherical grain silicon, and spherical grain silicon, wherein said first layer, said oxide layer, and said second layer form a laminate having an average sheet resistance and having a plurality of points each of which has a sheet resistance within 10% of said average sheet resistance.
- 22. A process for forming a silicon layer over a semiconductor substrate, said process comprising:
forming a first layer over said semiconductor substrate, said first layer being substantially composed of a material selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, cylindrical grain polysilicon, hemispherical grain silicon, and spherical grain silicon; forming an oxide layer upon said first layer having a thickness in a range from about 1 Angstrom to about 20 Angstroms; and forming a second layer upon said oxide layer, said second layer being substantially composed of a material selected from the group consisting of polysilicon, hemispherical grain silicon, spherical grain silicon, amorphous silicon, and monocrystalline silicon, said second layer having a plurality of points thereon, wherein thickness measurements at each said point on said second layer is within 7% of an average thickness of said second layer.
- 23. A process for forming a silicon layer over a semiconductor substrate, said process comprising:
providing a semiconductor substrate containing a dopant material positioned at first and second separate and substantially identical active regions in said semiconductor substrate; forming a first layer of silicon-containing material over said semiconductor substrate; oxidizing said first layer of silicon-containing material to form an oxide layer upon said first layer of silicon-containing material, said oxide layer having a thickness in a range from about 1 Angstrom to about 20 Angstroms, wherein, after said oxidation of said first layer of silicon-containing material, said first and second active region of said semiconductor substrate are substantially identical and unchanged by said oxidizing of said first layer of silicon-containing material; and forming a second layer of silicon-containing material upon said oxide layer.
- 24. A process for forming a polysilicon layer over a semiconductor substrate, said process comprising:
providing a semiconductor substrate including a monocrystalline silicon layer that has an exposed surface; forming an oxide layer having a substantially uniform thickness in a range from about 1 Angstrom to about 20 Angstroms upon said exposed surface of said monocrystalline silicon layer by exposing said monocrystalline silicon layer to an oxidizer including at least one oxidizing agent selected from the group consisting of diatomic oxygen, ozone, and hydrogen peroxide, wherein said oxide layer is formed in an oxidizing process conducted at a temperature less than about 200° C.; and forming a polysilicon layer upon said oxide layer.
- 25. A process as recited in claim 24, wherein said oxide layer has a thickness of from about one to about nine molecules of silicon dioxide.
- 26. A process as recited in claim 24, wherein said process forms a structure comprising each of said monocrystalline silicon layer, said oxide layer, and said polysilicon layer, said structure having an average sheet resistance, said structure further having sheet resistance measurements at each point on said structure, all of which are within 10% of said average sheet resistance.
- 27. A process for forming a silicon layer over a semiconductor substrate, said process comprising:
forming a first polysilicon layer over said semiconductor substrate, said first polysilicon layer having an exposed top surface, said first polysilicon layer being doped with dopants at a concentration in a range from about 5×1019 atoms/cm3 to about 1×1021 atoms/cm3; forming a contact opening through said first polysilicon layer, said contact opening being defined in part by both of a contact surface on said semiconductor substrate and a sidewall surface of said first polysilicon layer; forming an oxide layer having a substantially uniform thickness in a range from about 1 Angstrom to about 20 Angstroms on each of:
said contact surface; said exposed top surface of said first polysilicon layer; and said sidewall surface of said first polysilicon layer, wherein said oxide layer is formed by exposing both of said first polysilicon layer and said contact surface to an oxidizer including at least one oxidizing agent selected from the group consisting of diatomic oxygen, ozone, and hydrogen peroxide, said oxide layer being formed in an oxidizing process being conducted at a temperature less than about 200° C.; and forming a second polysilicon layer upon said oxide layer, said second polysilicon layer covering said contact surface and said sidewall surface.
- 28. A process as recited in claim 27, further comprising, before forming said first polysilicon layer:
providing an electrically conductive layer upon said semiconductor substrate; and providing an electrically insulative layer upon said electrically conductive layer.
- 29. A process as recited in claim 27, wherein said oxide layer substantially prevents diffusion of said dopants from said first polysilicon layer into said second polysilicon layer.
- 30. A process as recited in claim 27, wherein said oxide layer has a thickness of from about one to about nine molecules of silicon dioxide.
- 31. A process as recited in claim 27, wherein said first polysilicon layer, said oxide layer, and said second polysilicon layer form a laminate having an average sheet resistance and having a plurality of points, wherein each said point has a sheet resistance within 10% of said average sheet resistance.
Parent Case Info
[0001] This application is a divisional of U.S. patent application Ser. No. 08/936,676, filed on Sep. 24, 1997, which is incorporation herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
08936676 |
Sep 1997 |
US |
Child |
09356637 |
Jul 1999 |
US |