The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, gate structures including one or more layers, referred to as gate stacks, are often used in transistors. Gate stacks may experience breaking/peeling issues during later processing, such as a post ion-implantation photoresist striping process. Although existing methods of fabricating semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Improvements in this area are desired.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
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The semiconductor device precursor 200 may also include various p-type doped regions and/or n-type doped regions, such as n-well and p-well, implemented by a process such as ion implantation and/or diffusion.
The semiconductor device precursor 200 may also include various isolation features 212. The isolation features 212 separate various device regions in the substrate 210. The isolation features 212 include different structures formed by using different processing technologies. For example, the isolation features 212 may include shallow trench isolation (STI) features. The formation of a STI may include etching a trench in the substrate 210 and filling in the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench. A chemical mechanical polishing (CMP) may be performed to polish back excessive insulator materials and planarize the top surface of the isolation features.
In the present embodiment, the semiconductor device precursor 200 includes a plurality of protrusion structure 220 formed over a surface of the substrate 210. In one embodiment, the protrusion structure 220 is polysilicon gate stack. As an example, the polysilicon gate stack 220 may include a dielectric layer 222 and a polysilicon layer 224. The dielectric layer 222 includes silicon oxide, silicon nitride, or any other suitable materials. The protrusion structure 220 may be formed by a procedure including deposition, photolithography patterning, and etching processes. The deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable methods, and/or combinations thereof. The photolithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The etching processes include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching).
The following description will be directed to the polysilicon gate, it being understood that various types of protrusion structures and various processes can benefit from the present invention.
The semiconductor device precursor 200 may also include sidewall spacers 226 formed on the sidewalls of the polysilicon gate 220. The sidewall spacers 226 may include a dielectric material such as silicon oxide. Alternatively, the sidewall spacers 226 may include silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The sidewall spacers 226 may be formed by deposition and dry etching processes known in the art.
In one embodiment, the semiconductor device precursor 200 also includes source/drain (S/D) features 240 in the substrate 210, separated by a respective polysilicon gate 220. As an example, the S/D feature 240 is formed by recessing a portion of the substrate 210 to form S/D recessing trenches and epitaxially growing a semiconductor material layer in the S/D recessing trenches. The semiconductor material layer includes element semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloy, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). The epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The S/D features may be formed by one or more epitaxy or epitaxial (epi) processes. The S/D features may be in-situ doped during the epitaxy process.
Source and drain features are often swapped, depending on the transistor's eventual use and electrical configuration. Therefore, the terms “source” and “drain” are deemed to be interchangeable.
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The ion implantation process is performed at a suitable energy and dosage to achieve desired characteristics of the integrated circuit device. For example, an ion-implant dosage is about 3×1010 ions/cm2. For another example, ion-implant energy is about 400 keV. The ion-implantation process may cause physical and chemical changes in the patterned photoresist layer 310 and result that a portion of the patterned photoresist layer 310 is hardened (designated as a portion 410 in
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A spin-and-dry process may be involved in the wet etching process. Spin and dry processes often present difficulties such as a protrusion structure breaking or peeling during the spinning process. In the present embodiments, however, such difficulties have been significantly reduced or eliminated.
In another embodiment, the patterned photoresist layer 310 covers the second region and exposes the first region. Then similar steps of 106-110 are implemented. In yet another embodiment, steps 104-108 can be repeated multiple times.
Additional steps can be provided before, during, and after the method 100, and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method 100.
Based on the above, the present disclosure offers methods for removing photoresist layer after an ion-implantation. The method employs a two-stage-striping process that performing a low temperature dry strip first to substantially remove a hardened portion of a photoresist layer formed in the ion-implantation, then followed by a wet etch to remove remaining photoresist layer. The method has demonstrated reduction of protrusion structure breaking/peeling.
The present disclosure provides many different embodiments of fabricating a semiconductor device that provide one or more improvements over the prior art. In one embodiment, a method for fabricating a semiconductor device includes providing a substrate. The substrate has protrusion structures. The method also includes forming a patterned photoresist layer over the substrate, including covering the protrusion structures. The method also includes applying an ion-implantation to the substrate, including the patterned photoresist layer. Therefore an outer portion of the patterned photoresist layer formed a hardened portion. The method also includes performing a two-stage-striping process to remove the patterned photoresist layer. The two-stage-striping process is to perform a low-temperature-dry-etch first to substantially remove the hardened portion of the patterned photoresist layer, thereby leaving a remaining portion of the patterned photoresist layer. Then it is followed by a wet etch to remove the remaining patterned photoresist layer.
In another embodiment, a method for fabricating a semiconductor device includes providing a substrate providing a substrate. The substrate includes a first region and a second region. The substrate also includes a gate structure disposed in the first region. The method also includes coating a photoresist layer over the substrate, patterning the photoresist layer to cover the first region and expose the second region, applying an ion-implantation to the substrate, including the first region. A hardened portion is formed on an outer portion of the photoresist layer during the ion-implant. The method also includes after the ion-implantation, performing an etching process to remove the patterned photoresist layer. The etching process is configured to perform a low-temperature dry etching first to substantially remove the hardened portion of the photoresist layer. Then it followed by a wet etching process to remove remaining photoresist layer.
In yet another embodiment, a method for fabricating a semiconductor device includes providing a substrate having polysilicon gate stacks, forming a patterned photoresist layer over the substrate. The patterned photoresist layer covers a first region and un-cover a second region of the substrate. The polysilicon gate stack is covered by the patterned photoresist in the first region while another polysilicon gate stack is un-covered by the patterned photoresist in the second region. The method also includes applying an ion-implant to the substrate. An outer portion of the patterned photoresist layer formed a hardened portion during the ion-implant. The method also includes performing a two-stage-striping process to remove the patterned photoresist layer. The two-stage-striping process includes performing a low-temperature-dry-etch first to substantially remove the hardened portion of the patterned photoresist layer, thereby leaving a remaining portion of the patterned photoresist layer. Then it is followed by performing a wet etch to remove the remaining patterned photoresist layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.