Methods and apparatus for a current sensor having fault detection and self test functionality

Abstract

Methods and apparatus for an integrated circuit having a magnetic sensing element, a fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry to detect the fault. The integrated circuit includes a fault pin to indicate the fault condition.

Description

BACKGROUND

As known in the art, there are many safety critical applications for magnetic sensor integrated circuits (ICs). There are a variety of specifications directed to improving functional safety and achieving higher overall quality levels and lower field failure rates. For example, test modes for major functional parameters of an IC allow customers to implement test functionality prior to insertion on a printed circuit board, for example. However, after installation in a system or subsystem, such as an automobile, there are limited test opportunities to ensure that components are operating properly.

SUMMARY

Exemplary embodiments of the present invention provide methods and apparatus for a magnetic position sensing IC having a self-test feature for a fault function that improves functional safety levels. For example, test modes are desirable in an automobile to determine if an IC is functioning properly. Such test modes can improve functional safety in certain safety critical applications. The accelerator pedal in an automobile is an example of a safety critical application. If a linear, or nearly linear, magnetic sensing element, such as a Hall or magnetoresistance element, is used in the IC and does not operate properly, a potentially dangerous situation can arise.

Exemplary embodiments of the present invention provide a self-test feature using a fault pin of a linear Hall effect sensor for current sensing applications. A test mode can be invoked manually by a user or automatically, such as at start up, through an input signal under certain operating conditions. The IC responds and validates that the device is working properly. By improving testability, functional safety in current sensing applications is enhanced.

In one embodiment, a current sensor IC includes testing of a fault feature for determining when an applied magnetic field exceeds a threshold value. In a current sensing application, the current creates the magnetic field. When the current exceeds the threshold value, it may be desirable to shut off the source of the current in order to prevent damage to control electronics and hardware, and the like.

In one aspect of the invention, an integrated circuit comprises: a sensing element, fault detection module coupled to the magnetic sensing element, the fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry to detect the fault condition, and a fault pin to indicate the fault condition.

The integrated circuit can further include one or more of the following features: the sensing element comprises a magnetic sensing element, the magnetic sensing element comprises a Hall element, the sensing element comprises a magnetoresistance element, the fault condition includes a current level above a threshold, the integrated circuit comprises a linear current sensor, the integrated circuit comprises a magnetic field sensor, the fault condition includes a magnetic field above first threshold and/or below a second threshold, the fault pin is configured to receive input/output signals, the output signal to indicate the fault condition and the input signal to receive a self-test initiation signal, the self-test initiation signal comprises a given voltage level applied for at least a given time duration, the given voltage level comprises about vcc/2, the integrated circuit outputs a result of the self-test on the fault pin, the result comprises a voltage level indicative of pass/fail for the self-test, the fault detection module comprises a first comparator to detect a first fault condition and a second comparator to detect a second fault condition, the first fault condition includes a current level below a first threshold, and the second fault condition includes a current level above a second threshold, the self-test is terminated when a magnetic field above a flux threshold is detected, the integrated circuit comprises a package having exactly four pins, the integrated circuit comprises a package having a thickness of less than 1.1 mm, the fault detection module comprises a programmable window comparator, the integrated circuit comprises a linear current sensor, and/or the integrated circuit is disposed in a core of an element in a three-phase power system.

In another aspect of the invention, an integrated circuit comprises: a means for sensing a magnetic field, a means for detecting a fault condition coupled to the means for sensing a magnetic field, a means for self-testing the means for detecting a fault condition, and a means for outputting the detecting fault condition and a result from the self-testing means. In one embodiment, the integrated circuit further comprises the means for outputting the detecting fault condition and the result from the self-testing means comprises an input/output pin and/or the self-testing is terminated when a detected magnetic field is above a flux threshold.

In a further aspect of the invention, a circuit for linear current detection comprises: a sensing element to detect a magnetic field, an output pin to output a signal indicative of the sensed current, a fault detection module to detect a first fault condition and a second fault condition, the first fault condition including a current level above a first threshold and the second fault condition including a current level below a second threshold, the fault detection module including self-test circuitry to test detection of the first and second fault conditions, and a fault pin to output detection of the first and second fault conditions, to output a result of self-test, and to input a self-test initiation signal. In one embodiment, the circuit further includes the self-test is terminated when a detected magnetic field is above a flux threshold and/or the fault detection module comprises a programmable window comparator.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following description of the drawings in which:

FIG. 1 is a schematic representation of a current sensor having fault detection and self-test functionality in accordance with exemplary embodiments of the invention;

FIG. 2 is a pictorial representation of the current sensor of FIG. 1 in a core;

FIG. 3 is a schematic representation of a the current sensor of FIG. 1 forming a part of a three-phase power system;

FIG. 4 is a graphical representation of current versus output voltage to show a fault condition;

FIG. 5 is a schematic representation showing further detail of the current sensor of FIG. 1;

FIG. 6 is a circuit diagram of an exemplary comparator circuit that can form part of the sensor of FIG. 1;

FIG. 7 is a timing diagram showing fault signal voltage and output voltage over time;

FIG. 8 is a circuit diagram of an exemplary circuit to detect a self-test initiation signal;

FIG. 9 is a circuit diagram of an exemplary fault detection and self-test module;

FIG. 10 is a circuit diagram an alternative self-test circuit;

FIG. 11 is a schematic representation of an exemplary package for a current sensor; and

FIG. 12 is a schematic representation of a leadframe that can form a part of an IC.

DETAILED DESCRIPTION

FIG. 1 shows an exemplary embodiment of a programmable linear magnetic sensor IC 100 having a fault detection module 102 in accordance with exemplary embodiments of the invention. In one embodiment, the sensor IC 100 comprises a current sensor linear device with a 120 KHz bandwidth, for example. The sensor IC has an analog output voltage VOUT that is proportional to an applied magnetic field. In one embodiment, the sensor has a linear output that starts at Vcc/2 and swings in positive and negative directions depending on the polarity of the applied field.

The sensor IC senses current in a manner well known in the art. In general, a magnetic field sensing element, such as a Hall element 104, generates a voltage in response to an applied magnetic field. A dynamic offset cancellation module 106 ‘chops’ the signal and a signal recovery module 108 provides an output signal. Sensitivity control 110 and offset control 112 can be used to adjust the signals, as shown and described for example, in U.S. Pat. No. 7,923,996, and U.S. Patent Publication No. US2011/0018533, which are incorporated herein by reference. It is understood that other techniques can be used to meet the needs of a particular application.

The magnetic field sensing element 104 in this and other embodiments can be, but is not limited to, a Hall effect element, a magnetoresistance element, or a magnetotransistor. As is known, there are different types of Hall effect elements, for example, a planar Hall element, a vertical to Hall element, and a Circular Vertical Hall (CVH) element. As is also known, there are different types of magnetoresistance elements, for example, a semiconductor magnetoresistance element such as Indium Antimonide (InSb), a giant magnetoresistance (GMR) element, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ). The sensing element 104 may include a single element or, alternatively, may include two or more elements arranged in various configurations, e.g., a half bridge or full (Wheatstone) bridge. Depending on the device type and other application requirements, the sensing element 104 may be a device made of a type IV semiconductor material such as Silicon (Si) or Germanium (Ge), or a type III-V semiconductor material like Gallium-Arsenide (GaAs) or an indium compound, e.g., Indium-Antimonide (InSb).

As is known, some of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity parallel to a substrate that supports the magnetic field sensing element, and others of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity perpendicular to a substrate that supports the magnetic field sensing element. In particular, planar Hall elements tend to have axes of sensitivity perpendicular to a substrate, while metal based or metallic magnetoresistance elements (e.g., GMR, TMR, AMR) and vertical Hall elements tend to have axes of sensitivity parallel to a substrate.

As used herein, the term “magnetic field sensor” is used to describe a circuit that uses a magnetic field sensing element, generally in combination with other circuits. Magnetic field sensors are used in a variety of applications, including, but not limited to, an angle sensor that senses an angle of a direction of a magnetic field, a current sensor that senses a magnetic field generated by a current carried by a current-carrying conductor, a magnetic switch that senses the proximity of a ferromagnetic object, a rotation detector that senses passing ferromagnetic articles, for example, magnetic domains of a ring magnet, and a magnetic field sensor that senses a magnetic field density of a magnetic field.

Exemplary embodiments of the invention are applicable to a variety of sensing applications having a range of sending elements. Exemplary sensors include magnetic field, accelerometer, temperature, chemical, biological, strain, piezoelectric, etc. Exemplary embodiments of the invention are applicable to a wide range of applications hi which sensing magnetic fields generated by moving magnets or flowing current are desirable. For example, exemplary embodiments of the invention are useful for HEV (hybrid electric vehicle) inverter applications because it has a 120 KHz operating bandwidth, that allows the sensor to be used in the gap of a core to sense the inverter phase current.

FIG. 2 shows an exemplary sensor IC 200 having self-test functionality in the gap of a core CO in accordance with exemplary embodiments of the invention. The core CO concentrates the magnetic field flowing in a current carrying conductor that goes through the center of the core. FIG. 3 shows an exemplary current sensor IC 300 having self-test functionality for load phase monitoring in a three-phase application, such as a hybrid electric vehicle (HEV). In this configuration, inventive current sensors are useful in HEV inverter applications.

During an over-current event, such as that might be produced in the case of a short to GND is one of the motor phases of FIG. 3, the output voltage of the inventive sensor IC increases dramatically beyond the normal operating range. In one embodiment, the output voltage of the sensor swings close to the positive or negative rail, depending on the direction of the current flow under the fault condition. FIG. 4 shows a nominal current of about +/−375 Amps and a short that drives the output to about +925 Amps, which is close to the positive rail of the output. As can be seen, the sensor senses both positive and negative fields and currents.

By providing a digital fault output in the presence of faults, such as a short to ground, an interrupt can be generated for the micro controller monitoring the current sensors and controlling a motor or motors.

While an illustrative example is shown for a current sensor (+/−375 A while a 900+ A fault), it is understood that the current generates a magnetic field. In exemplary embodiments, the magnetic field can be programmed to different levels which in a current sensor may represent current levels, but in other applications may represent a magnetic field moving to a level or field outside of a desired range. In addition, while the example is directed to a bidirectional current, and therefore, a bidirectional magnetic field, a unidirectional magnetic field and currents are also contemplated. In addition, in one embodiment, a magnetic field or current level shifted from the zero level as desirable when a linear magnetic field sensor is used to detect the presence of a magnet for a position or height application, for example. Normal operation may be in the range of say, but not limited to, 50 G to 450 G or centered at 200 G+/−150 G. In such a case, a fault may be tripped if the field drops below 50 G or above 450 G, for example.

It is understood that features of exemplary embodiments of the invention may be useful in a variety of sensor types, such as integrated current sensors having a notched conductor, a magnetic field transducer, and a magnetic core, and current sensors having a magnetoresistance element coupled to a device supported on a silicon substrate, such as an amplifier.

FIG. 5 shows further detail of an exemplary embodiment of the fault detection module of FIG. 1. The fault detection module 200 monitors the analog output and includes a programmable window comparator module 202 with comparators to generate the fault output FAULT. In one embodiment, the fault detection module 200 detects a fault and activates the fault output FAULT. It is understood that the fault output FAULT can be readily set to the active state for either a positive (logical ONE) or negative (logical ZERO). In the illustrated embodiment, the fault output is shown as active low.

It is understood that the fault output FAULT can provide redundancy with other fault signals in the system, such as from a motor driver or micro-controller. This redundancy improves the overall control system functionality, such as the Automotive Safety Integrity Level (ASIL) applicable to safety levels in safety critical applications in autmobiles. For example, power steering and accelerator pedal position require higher levels of safety defined by ASIL.

In an exemplary embodiment, the fault detection module includes a self-test routine that can be initiated by the user to ensure that the sensor fault function is operating properly. In one embodiment, self-test is initiated by providing a given voltage level on the FAULT pin.

FIG. 6 shows an exemplary window comparator 600 that can form a part of the fault detection module of FIG. 5. Resistors R1, R2, and R3 determine trip points of first and second comparators 602, 604. In an exemplary embodiment, a reference voltage resistor can be programmable by employing R/2R ladder DACs, which are well known in the art, to set the desired window thresholds for detecting the fault. The circuit can be programmed to trip under the short condition of FIG. 4 and the fault output FAULT becomes active when a short circuit current, for example, is detected by the comparators.

In one embodiment, the fault can be detected as a positive or negative value using the respective comparators 602, 604. In the illustrated embodiment, the comparator output is configured for active low operation. If the first or second comparators 602, 604 have an active output, a switch 606 is activated to bring the fault output FAULT to ground.

In one embodiment, the fault pin FAULT comprises an input/output pin that enables initialization of the self-test function, as shown in FIG. 7. During a time when the magnetic field is near zero, meaning no current flows in the application, and therefore no magnetic field, the FAULT output pin can be pulled to Vcc/2 to initiate self test of the fault detection functionality. In the illustrated embodiment, during time t_ASILI the voltage on the FAULT pin is pulled Vcc/2, shown as V_ASILI. During time t_ASILH, self-test is performed. The device pulls the FAULT pin output low during this time to acknowledge the device received the command to initiate self-test during time tASILI During time t_ASILR, the results of the self-test are output on the FAULT pin, shown as Vcc for a self-test pass and V_ASILO for self-test fail.

As noted above, and shown in FIG. 7, the output voltage Vout will be at V_OUTOG when no magnetic field is present. During normal operation, the output voltage Vout can vary from a maximum V_OUTG(max) and a minimum of V_OUTG(min). VFPSP and VFNSP refer to the positive full scale output voltage and negative full scale output voltage.

As shown in FIG. 8, the device can sense Whether the Fault pin has been pulled to about Vcc/2, shown as V_ASILI, at the beginning of time interval t_ASILI in FIG. 7, and no magnetic field is detected by the Hall element. In the illustrated embodiment 800, a signal from the Hall element is provided to first and second comparators 802, 804, which have respective reference voltages defined by the values of R1, R2, and R3 that determine what is considered ‘zero’ magnetic field. That is, the magnetic field should be less than some value. In one embodiment, resistor R2 is adjustable for setting the comparator reference voltages, e.g., a programmable window comparator. The outputs of the comparators 802, 804 are provided to an input of an AND gate 806, of which the output is provided to a clocked counter 808. The Fault pin voltage is input to third and fourth comparators 610, 812, which have respective reference voltages determined by the values of R4, R5, R6. The comparator 810, 812 outputs are provided to the AND gate 806 input. With this arrangement, when the voltage from the Hall element is around zero, and the Fault pin is pulled to about Vcc/2, the self-test function is enabled after a time defined by the counter 808.

FIG. 9 shows an exemplary circuit implementation 900 of a fault detection module and self-test functionality. After a timeout period of the counter 808 (FIG. 8), shown as tASILI in FIG. 7, the device then enters the self-diagnostic mode. The counter 808 prevents noise or glitches from causing the part to go into the test mode. The timeout tASILI can be set for a desired period of time, such as a few microseconds. It is understood that the timeout tASILI can be set to any practical amount of time that is desirable to meet the needs of a particular application.

The sensor ‘sees’ that the self-test command was received by the output of the fault pin pulled to GND for time tASILH in FIG. 7. The chip ‘sees’ this because during a time when there is no magnetic field/current the FAULT output was held at Vcc/2 by for time tASILI from counter 808. The active pull down by the IC acknowledges that the command was received. If the output does not go low then the command to perform the self-test is not ‘seen.’ When control of the fault pin is released, the device takes control of the output pin and actively holds it to GND for time tASILH, which communicates that the self test command was received. The time tASILH should be long enough for the device to complete the diagnostic test in order to report the results during the time tASILR, as shown in FIG. 7.

In one embodiment, the self-test functionality is implemented as shown in FIG. 9. An ASIL input command detection module 901 can be configured as shown and described in conjunction with FIGS. 7 and 8. Once the ASIL command is detected, a test control module 902 pulls the FAULT output to GND with a control signal input 904 to an OR gate 906. The test control module 902 implements the following sequence of testing while maintaining the output low (see FIG. 7) by controlling the input to the OR gate.

During self-test, the test control module 902 closes switch position 5 of a first switch SW1 so the output of a 3-position second switch SW2. Under normal operation, the first switch SW1 has position 6 closed to receive the Hall signal.

The test control module 902 controls the second switch SW2 to one of position 1 (V+), position 2 (V+/2), or position 3 (GND). The test control module 902 cycles through these connections to verify that at SW2 positions 1 and 3 the output of the fault comparator is low (fault condition present), and that at position 2 the output of the fault comparator is high (no fault). In one embodiment, the switches SW1, SW2 are provided on the IC.

Once this sequence is completed the comparator circuitry has been tested and the results can be communicated after the timeout of tASILH (see FIG. 7). More particularly, if self-test fails the device can continue to pull the output FAULT low for a period of time tASILR. In an alternative embodiment, if the self-test fails the sensor can latch the failure on the output. In the illustrated embodiment, the device holds the fault output low for a selected period of time and releases the output to enable a resumption of normal operation and further self-test. For example, it may be desirable to re-run a self-test in the case where a failure due to a glitch or noise pulse resulting a false positive test.

If self-test is successful the device drives the output HI during time tASILR labeled as self-test passing in FIG. 7. Once the self-test result during time tASILR ends, test control module 902 releases the FAULT pin by reconnecting the Hall input voltage to the fault comparator by connecting to the first switch SW1 to position 6 and clearing the input to the OR gate to a logic low to assume normal operation.

With this arrangement, the device provides a self-test diagnostic that allows for each of the three states of the comparator to be tested. The self-test can improve the functional safety level of the entire system and allow improved levels of safety according to ISO26262, for example.

In one embodiment, in the event a sensed magnetic field increases above a given threshold as detected by the Hall circuitry, the device exits test mode.

In another embodiment, the device includes circuitry to test the accuracy of the programmed fault thresholds by controlling switch positions 1 and 3 voltages close to the programmed fault thresholds and testing a short distance away from both of the thresholds. For example, say the fault threshold is programmed to a value 200 mV below V+. References of V+−200 mV+/−x mV can be used to test that the comparator switches low at +x mV and does not switch at −x mV. The value ‘x’ in mV can be selected to meet the needs of a particular application. It is understood that the smaller the value of ‘x’, the more accurately the switchpoints are tested.

An alternate embodiment 1000 of testing the window comparators is shown in FIG. 10 that tests in parallel instead of sequentially. The logic gates G1-3 and comparators CP1, CP2 must function correctly for the ASIL test to pass. During normal operation only the NAND gate G3 following the comparators CP1, CP2 is used in the Fault signal path. During normal Fault detection operation the window references RefH and RefL are used as thresholds to detect a fault condition. In ASIL test mode after the required time tASILI described above verifies that an ASIL test is being requested, the references are switched to TestRefH and TestRefL. Also, at that time, a MUX is switched to detect the alternate logic path. TestRefH and Test RefL need only be of a value that the comparators should trip as described above. In one embodiment, there is a cross connect of the two normal operation references such that TestRefH=RefL and TestRefL=RefH. This ensures that the comparators CP1, CP2 have outputs indicative of a Fault condition.

In normal Fault detection operation the switches SW1, SW2 are connected as shown and the ASIL_Valid signal is LO. The references RefH and RefL are set so that the comparator CP1, CP2 outputs are high if the device is operating in the desired output range. The Boolean equation indicated as Mux0 path is valid and point C goes high if either points A or B (the outputs of the comparators) go low indicating that a Fault has occurred.

During the ASIL test mode after the ASIL test request is valid for the period tASIL, the switches SW1, SW2 connect the comparator CP1, CP2 inputs to new reference levels TstRefH and TestRefL. The MUX 1 input is also connected to point C so the MUX 1 Boolean equation is valid in this ASIL test mode. Now both comparator CP1, CP2 outputs must be low for point C to go high. If the condition TstRefH<Out<TestRefL is met, the outputs of the comparators CP1, CP2 go low and if the logic gates are also functioning correctly then through the Boolean function C goes HI signaling that the comparators and the logic are functioning correctly.

FIG. 11 shows an exemplary device packaged in a 4 lead KT SIP. It is understood that the IC can comprise any suitable package. In one embodiment, the package has a thickness of less than about 1.1 mm. It is understood that it is desirable to minimize the thickness of the package.

It is understood that a variety of packages can be used to meet the needs of a particular application. For example, a package of the type shown and described in U.S. Pat. No. 6,781,359, which is incorporated herein by reference, can be used.

FIG. 12 shows an exemplary split leadframe 1200 configuration in which a leadframe 1202 has a region 1204 cutout from the rest of the leadframe. A magnetic sensing element 1206 is located within the region 1204 to prevent Eddy current formation in the vicinity of the sensing element. A die 1208 can be supported by the leadframe.

Having described exemplary embodiments of the invention, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

Claims

1. An integrated circuit, comprising: a sensing element;fault detection module coupled to the sensing element, the fault detection module including circuitry to detect and output a fault condition and circuitry to perform self-test operation of the circuitry to detect the fault condition; anda fault pin to output the fault condition and to receive a self-test command,wherein the fault condition includes a magnetic field is above a first threshold and/or below a second threshold,wherein the self-test is terminated before completion when the magnetic field is above a flux threshold, andwherein the self-test operation is initiated only when the magnetic field is below a certain level associated with no magnetic field present.

2. The integrated circuit according to claim 1, wherein the sensing element comprises a magnetic sensing element.

3. The integrated circuit according to claim 2, wherein the magnetic sensing element comprises a Hall element.

4. The integrated circuit according to claim 2, wherein the magnetic sensing element comprises a magnetoresistance element.

5. The integrated circuit according to claim 1, wherein the fault condition includes a current level above a threshold.

6. The integrated circuit according to claim 1, wherein the integrated circuit comprises a linear current sensor.

7. The integrated circuit according to claim 1, wherein the integrated circuit comprises a magnetic field sensor.

8. The integrated circuit according to claim 1, wherein a self-test initiation signal comprises a given voltage level applied for at least a given time duration.

9. The integrated circuit according to claim 8, wherein the given voltage level comprises about vcc/2.

10. The integrated circuit according to claim 1, wherein the integrated circuit outputs a result of the self-test on the fault pin.

11. The integrated circuit according to claim 10, wherein the result comprises a voltage level indicative of pass/fail for the self-test.

12. The integrated circuit according to claim 1, wherein the fault detection module comprises a first comparator to detect a first fault condition and a second comparator to detect a second fault condition.

13. The integrated circuit according to claim 12, wherein the first fault condition includes a current level below a first threshold, and the second fault condition includes a current level above a second threshold.

14. The integrated circuit according to claim 1, wherein the integrated circuit comprises a package having exactly four pins.

15. The integrated circuit according to claim 1, wherein the integrated circuit comprises a package having a thickness of less than 1.1 mm.

16. The integrated circuit according to claim 1, wherein the fault detection module comprises a programmable window comparator.

17. The integrated circuit according to claim 1, wherein the integrated circuit comprises a linear current sensor.

18. The integrated circuit according to claim 1, further comprising a three-phase power system, wherein the integrated circuit is disposed in a core of an element in the three-phase power system.