Claims
- 1. A test system, comprising:
a tester configured to test a set of components and generate test data for the set of components; and an outlier identification system configured to receive the test data from the tester and automatically identify outliers in the test data according to at least one selected outlier identification algorithm, wherein the at least one selected outlier identification algorithm is automatically selected from a plurality of candidate outlier identification algorithms.
- 2. A test data analysis system for analyzing test data for a set of components fabricated and tested using a fabrication process, comprising:
a memory for storing the test data; and an outlier identification system having access to the memory and configured to identify outliers in the test data according to an outlier identification algorithm, wherein the outlier identification system is configured to automatically select the outlier identification algorithm from a plurality of outlier identification algorithms according to at least one characteristic of the test data.
- 3. A computer-implemented method for testing components fabricated and tested according to a fabrication process, comprising:
obtaining test data for the components; selecting an outlier identification algorithm according to selected characteristics of the test data; and automatically identifying outliers in the test data according to the selected outlier identification algorithm.
- 4. A medium storing instructions executable by a machine, wherein the instructions cause the machine to execute a method for analyzing test data comprising:
obtaining test data for the components; automatically selecting at least one outlier identification algorithm according to at least one characteristic of the test data; and identifying an outlier in the test data using the at least one selected outlier identification algorithm.
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is:
[0002] a continuation-in-part of U.S. patent application Ser. No. 10/730,388, filed on Dec. 7, 2003, entitled METHODS AND APPARATUS FOR DATA ANALYSIS, which is a continuation-in-part of U.S. patent application Ser. No. 10/367,355, filed on Feb. 14, 2003, entitled METHODS AND APPARATUS FOR DATA ANALYSIS, which is a continuation-in-part of U.S. patent application Ser. No. 10/154,627, filed on May 24, 2002, entitled METHODS AND APPARATUS FOR SEMICONDUCTOR TESTING, which is a continuation-in-part of U.S. patent application Ser. No. 09/872,195, filed on May 31, 2001, entitled METHODS AND APPARATUS FOR DATA SMOOTHING, which claims the benefit of U.S. Provisional Patent Application No. 60/293,577, filed May 24, 2001, entitled METHODS AND APPARATUS FOR DATA SMOOTHING; U.S. Provisional Patent Application No. 60/295,188, filed May 31, 2001, entitled METHODS AND APPARATUS FOR TEST DATA CONTROL AND ANALYSIS; and U.S. Provisional Patent Application No. 60/374,328, filed Apr. 21, 2002, entitled METHODS AND APPARATUS FOR TEST PROGRAM ANALYSIS AND ENHANCEMENT;
[0003] claims the benefit of U.S. Provisional Patent Application No. 60/483,003, filed Jun. 27, 2003, entitled DEVICE INDEPENDENT WAFERMAP ANALYSIS; and
[0004] claims the benefit of U.S. Provisional Patent Application No. 60/546,088, filed Feb. 19, 2004, entitled DYNAMIC OUTLIER ALGORITHM SELECTION FOR QUALITY IMPROVEMENT AND TEST PROGRAM OPTIMIZATION,
[0005] and incorporates the disclosure of each application by reference. To the extent that the present disclosure conflicts with any referenced application, however, the present disclosure is to be given priority.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60293577 |
May 2001 |
US |
|
60295188 |
May 2001 |
US |
Continuation in Parts (4)
|
Number |
Date |
Country |
| Parent |
10730388 |
Dec 2003 |
US |
| Child |
10817750 |
Apr 2004 |
US |
| Parent |
10367355 |
Feb 2003 |
US |
| Child |
10730388 |
Dec 2003 |
US |
| Parent |
10154627 |
May 2002 |
US |
| Child |
10367355 |
Feb 2003 |
US |
| Parent |
09872195 |
May 2001 |
US |
| Child |
10154627 |
May 2002 |
US |