Patent Application
20080296562
Carbon nanotubes (CNT) hold promise as a device material that is inherently small (˜1-2 nm), inherently one-dimensional with near perfect crystalline order allowing ballistic transport over relatively large distances. The utility of these features is such that CNTs allow for inherently fast device operation. Projected device operating speeds are up to a terahertz (THz). The one-dimensional nature of the CNT material allows only discrete quantized states that lead to high-linearity at much lower power than current electronic devices.
One implementation of CNTs that take advantage of these properties is a CNT field-effect transistor (FET). A typical geometry of a CNT FET includes a CNT connecting two metallic pads that serve as drain and source. A gate dielectric is deposited on top of the CNT. Additional metal is deposited above the gate dielectric to serve as the gate metal. The gate dielectric electrically isolates the CNT from the additional metal. A wiring dielectric is deposited above the gate, drain and source and the entire structure is on an insulating substrate.
Unfortunately, CNT FETs currently suffer from a number of limitations. For example, in the above configuration, the length of the CNT must be at least the width of the gate layer plus twice the distance allowed for layer-to-layer alignment error (i.e., twice the distance of the layer-to-layer (e.g., drain-to-gate and gate-to-source) spacing). These requirements can reduce device performance since (1) the CNT may not allow ballistic transport for the entire distance between the drain and source and (2) the length that the gate voltage can couple to the CNT is only a fraction of the length of the CNT, reducing the responsiveness of the CNT FET.
Moreover, current CNT fabrication methods have certain disadvantages. For example, issues arise during the growth of CNTs that prevent or limit larger-scale integration of CNTs. As a CNT begins its growth, typically from an iron particle that serves as a catalyst, the nanotube “wraps” in upon itself in a variety of modes. In other words, various nanotubes may begin wrapping at different times and in different manners. The wrapping of the nanotube is known as the nanotube's “chirality”. The chirality of each CNT dictates the electronic properties of the CNT. In practice, the variation in chirality of CNTs dictates that approximately two-thirds of the CNTs are semi-conducting and one-third are metallic. In device, such as CNT FET, fabrication, the metallic CNTs will short out the desired semi-conducting CNTs.
Additionally, in order to fabricate a device (e.g., a CNT FET) to take advantage of the above-described properties of CNTs, a thin, high-dielectric, gate oxide is often included. The gate oxide may be placed either above or below the CNTs in a typical integrated circuit implementation of such a device. However, depositing an oxide on to CNTs can be problematic. For example, the oxygen, often activated oxygen in deposition processes, may react with and damage the CNTs. Likewise, growing CNTs on the oxide material, where the oxide is placed below the CNTs, can also be problematic. For example, a reduced atmosphere is often used in the growth of CNTs (e.g., such as when chemical vapor deposition (CVD) is used to grow CNTs), and the reduced atmosphere may decompose the oxide, destroying its dielectric integrity.
An advantage of the embodiments described herein is that they overcome disadvantages of the prior art.
For example, some embodiments described herein overcome the limitations of CNT FETs. These advantages and others are achieved by a method of fabricating self-aligned carbon nanotube (CNT) field-effect transistors (FET) includes providing a substrate that is fabricated from a ultraviolet (UV) radiation transparent material, placing one or more CNTs on a front-side of the substrate, depositing a UV radiation-opaque material on a portion of the CNTs as FET drain and source, applying photoresist (PR) on a portion of the CNTs not covered by UV radiation-opaque material and on top of the UV radiation-opaque material, illuminating a bottom-side of the substrate with UV radiation, whereby the UV radiation passes through the substrate and exposes a portion of the PR to the UV radiation, developing the UV radiation-exposed PR, whereby the developed PR is removed, depositing a bi-layer, defining a FET gate, and applying a PR mask. These advantages are also achieved by a CNT FET manufactured according to the method.
Likewise, some embodiments described herein overcome the effects of chirality. These advantages and others are achieved by a method of selectively etching metallic CNTs. The method includes providing a substrate, placing a plurality of CNTs on a surface of the substrate, in which the CNTs include semi-conducting CNTs and metallic CNTs, depleting conduction electrons in the semi-conducting CNTs, whereby at least some of the semi-conducting CNTs are prevented from conducting, and burning out the metallic CNTs.
These advantages and others are also achieved by an apparatus for selectively etching metallic CNTs. The apparatus includes a substrate, a plurality of CNTs including metallic CNTs and semi-conducting CNTs, an insulating layer, a conducting layer, a voltage source, in which the voltage source bias the conducting layer so as to deplete the semi-conducting CNTs of conduction electrons, and a microwave source, in which the microwave source applies microwave radiation to the CNTs, causing the metallic CNTs to conduct current until burning out.
Additionally, some embodiments described herein overcome the oxide deposition problems. These and other advantages may be achieved by a method of fabricating an oxide in a carbon nanotube (CNT) device. Embodiments of the method include providing a substrate, depositing an anodizable metal layer on a surface of the substrate, placing one or more CNTs on the anodizable metal layer, and anodizing the anodizable metal layer beneath the one or more CNTs, whereby an oxide layer is created beneath the one or more CNTs.
These and other advantages may also be achieved by an apparatus for fabricating an oxide in a carbon nanotube (CNT) device. Embodiments of the apparatus include a substrate, an anodizable metal layer on a surface of the substrate, one or more CNTs placed on the anodizable metal layer, an anode, a electrolytic solution submerging the anode and the anodizable metal layer, and a voltage source connected to the anode and the anodizable metal layer, in which the voltage source applies a voltage to the anode and the anodizable metal layer, anodizing the anodizable metal layer to produce an oxide beneath the one or more CNTs.
The detailed description will refer to the following drawings, wherein like numerals refer to like elements, and wherein:
Various methods and apparatus for overcoming the problems identified above are described herein. The embodiments described herein enable the fabrication of improved CNT devices, including improved CNT FETs and other integrated circuits. Certain of the various methods and apparatus described herein may be combined in order to fabricate improved CNT devices with the benefits from each.
Self-Aligned CNT FET Fabrication Processes
With reference now to
Layer-to-layer spacing may be reduced by overlapping the gate metal with the drain and the source in the CNT FET. However, this is problematic as the gate dielectric is typically thin and would likely not provide dielectric coverage as the gate metal crosses the drain or source edge. Another problem is the overlapping area of gate and drain (or gate and source) would create a relatively large and parasitic capacitance.
In embodiments of the method of fabricating self-aligned CNT FETs, a substrate material that is transparent to ultraviolet (UV) radiation is used. Such substrate material includes but is not limited to quartz. In such embodiments, using a UV transparent substrate allows a layer to be patterned on a front-side of the substrate with a material opaque to UV radiation (e.g., titanium or gold) and, after coating the front-side of the substrate with photoresist (PR) (photoresist is a light sensitive material, typically a liquid polymeric material, used in several industrial processes, such as photolithography and photoengraving to form a patterned coating on a surface), the PR is exposed with UV radiation through the back-side of the substrate. In this matter the pattern is exposed with the UV radiation through the UV radiation transparent substrate. The initial UV radiation opaque layer (e.g., gold layer) serves as a mask blocking the UV radiation exposure and the PR. Only the area of the PR without the opaque layer will be exposed and can be developed away. A variety of PRs, particularly useful as deep UV (DUV) photoresists, may be used, such as polyhydroxystyrene-based polymers with a photoacid generator providing a solubility change, benzene-chromophore and diazonaphthoquinone-novolac resin (DNQ-novalec) mixtures, etc.
With reference again to
A PR masking is applied on the CNTs on the substrate surface (the substrate front-side) and defined with standard photolithography, block 16. Standard photolithography generally includes four steps: PR coating, exposure, development, and hard-baking. In the PR coating, a substrate, is coated with PR. The PR is the material that an image will be transferred to during the photolithography process and is UV-sensitive. The coating process is typically performed by spinning the substrate at speeds between 1000 and 5000 rpm. PR is deposited onto the substrate surface during this dynamic movement to ensure even coating over the entire substrate surface. Other alternatives include using dry film PRs, which can be laminated into place to create the photo-patternable surface. Once the substrate has been coated with PR, the exposure includes exposing the substrate on an exposure tool. For example, UV radiation may be shined through a glass plate which is partially coated with chrome or other metal patterns on its surface. Alternatively, a soda lime plate may be used This plate, termed a photomask or mask, has the master image of the device on it. By shining UV radiation through the mask and onto the substrate, individual areas of the PR are selectively exposed to light to define the PR mask (i.e., the areas not masked or blocked by the metal patterns on the plate). This exposure causes a chemical change in the PR. Development includes immersing the exposed substrate in a developer solution. Developer solutions are chemical solutions that are usually aqueous and will dissolve the areas of the PR that were exposed to light, leaving the defined PR mask pattern defined by the photomask. After development, the substrate is baked in an oven or hot plate at temperatures generally between 100-120° C. to perform the hard-bake. This hard-bake drives off liquids that may have been absorbed on the substrate and crosslinks the remaining PR. Crosslinking the PR mask increases mechanical and chemical stability of the material, allowing it to be used in further substrate processing.
The PR masking masks a portion of the CNTs and the substrate surface. Using a material that is opaque to UV radiation, drain and source metal is deposited on the portions of the CNTs and substrate surface not masked by the PR, block 18. The initial PR may be lifted off. Exemplary drain and source metal include, without limitation, Titanium (Ti) and Gold (Au). Additional PR is applied, such as by being spun on (e.g., by spinning substrate as described above), block 20. The additional PR is applied on the portions of the CNT and substrate not covered by the UV-opaque material and on top of the UV-opaque material itself.
The PR is exposed to UV radiation through the bottom (i.e., back-side) of the substrate, block 22. The PR may be exposed to UV radiation by illuminating, flooding or bombarding the substrate bottom with UV radiation since the UV-opaque drain and source metal will only allow exposure of a portion of the PR not blocked by the UV-opaque material. The UV radiation passes through the UV-transparent substrate. The exposed PR is developed out (e.g., as described above in standard photolithography process), block 24. A barrier layer (e.g., Aluminum Oxide (Al2O3), Titanium Oxide (TiO2), Silicon Oxide (SiO2), etc.) and gate metal (e.g., Ti, Au, etc.) are deposited, block 26. The deposited layers are lifted-off over the PR, block 28. Lift-off is where the metal deposited on a making layer of PR is removed when the underlying PR is removed, typically in acetone. The metal deposited where there was not PR will remain. Additional PR is deposited to mask for gate definition, block 30. The gate metal may be etched to define the gate, block 32.
With reference now to
With reference now to
Selective Etching of Metallic CNTs
With reference now to
Currently, the problem of metallic CNTs being created is skirted by growing CNTs as normal and then selecting and studying devices that only have useful, semi-conducting CNTs. However, this method is not easily adaptable for industrial manufacturing processes. In order to integrate CNT devices into a manufacturable process, a method is needed to eliminate metallic CNTs. Approaches have been proposed to engineer the size and shape of the catalyst, to multiply and re-grow a known semi-conducting CNT and to take advantage of a slight chemical selectivity as a function of chirality. These approaches have their own difficulties, unfortunately, and still may not entirely eliminate all metallic CNTs. The presence of any metallic CNTs has a direct and deleterious impact on device yield.
The method of selectively etching metallic CNTs described herein globally eliminates the undesirable metallic CNTs. The method may be used with any growth or spin-on technique and removes the eliminates metallic CNTs after the CNTs have been grown or spun-on. The embodiments shown take advantage of differing transport properties of CNTs to generate a current in the metallic CNTs. A relatively small current is enough to burn out a metallic CNT much like a filament in a light bulb that receives too much current. Temperatures in CNTs may be come as high as 1500 C with currents of only a few tenths of a microampere. In embodiments, the burning out affect may be enhanced by purposefully putting a source of oxygen in intimate contact with the CNT in the form of either a gas or an overlying oxide film.
With reference again to
Contacts are connected or applied to the conducting layer, block 110. The contacts enable a voltage to be applied to the conducting layer. A voltage is applied to the conducting layer so that the conducting layer is biased to a sufficient voltage to deplete the conduction electrons only in the semi-conducting CNTs, block 112. For example, a voltage of 1-10V may be applied. Depleting the conduction or conducting electrons in the semi-conducting CNTs prevents the semi-conducting CNTs from conducting. A microwave source is provided, block 114, and microwaves are applied by the microwave source to the CNTs, block 116. The metallic CNTs will conduct and will “burn-out” in response to the microwave radiation, block 118. Since the semi-conducting CNTs are prevented from conducting, only the metallic CNTs will conduct, leaving the semi-conducting CNTs undamaged. The insulting layer and conducting layer are removed, block 120. After the removal of these layers, the CNTs may be continue to be processed and fabricated as a CNT FET, e.g., as described above with reference to
With continuing reference to
With reference now to
CNT FET Gate-Oxide Fabrication Processes Using Anodization
With reference now to
With reference to
Contacts to the CNTs may be protected, e.g., by standard photolithography, block 208 (the contacts are the metal that makes electrical contact to the CNTs, typically made of Au, Ti/Au or Pd). For example, PR may be applied to contacts on the CNT as a mask to protect the contacts. The defined PR covers the areas that you do not want to be in contact with the anodization solution. A voltage source and an anode are provided, block 210, and the source is connected to the anodizable metal layer and the anode, block 212. The anode and the entire device structure (i.e., substrate with anodizable metal and CNTs), or least a portion sufficient to submerge the anodizable metal layer and the adjacent portion of the substrate, is placed into an electrolytic solution, block 214. The electrolytic solution may be, for example, ammonium pentaborate or other electrolytic solutions. A voltage is then applied to the anode and the anodizable metal layer to anodize the anodizable metal layer underneath the CNTs, block 216. The voltage may be chosen to anodize a certain amount of anodizable metal. For example, if the anodizable metal layer is Nb, the Nb will anodize at the rate of 2.3 nm of niobium oxide per volt. The voltages applied to the anode and the anodizable metal layer will have opposing polarity (e.g., negative voltage to the anodizable metal layer and positive voltage to the anode). The anodization of the anodizable metal layer results in a sealed oxide with typically excellent dielectric integrity directly between the CNTs and any remaining unanodized metal. The unanodized metal layer may then serve as a gate metal in the final device. Since CNTs make poor electrical contact with the anodizable metal layer and have much higher resistivities, the CNT will not react and will not be anodized.
With continuing reference to
With reference now to
With reference now to
The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that many variations are possible within the spirit and scope of the invention as defined in the following claims, and their equivalents, in which all terms are to be understood in their broadest possible sense unless otherwise indicated.
