Methods and apparatus for providing a booth multiplier

Abstract

Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is −2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.

Description

DESCRIPTION OF THE DRAWINGS

For the purposes of illustration, there are forms shown in the drawings that are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

FIG. 1 is a block diagram of a multiplier circuit operable to produce partial products in connection with the multiplication of two binary numbers in accordance with one or more embodiments of the present invention;

FIG. 2 is a detailed circuit diagram of a radix 4 encoder circuit suitable for implementing one or more circuit blocks of the multiplier circuit of FIG. 1;

FIG. 3 is a truth table illustrating the operation of the encoder circuit of FIG. 2 in converting radix 2 binary number groups into radix 4 encoded numbers and also into Booth encoded bits;

FIG. 4 is a detailed circuit diagram of a selector circuit suitable for implementing one or more circuit blocks of the multiplier circuit of FIG. 1;

FIG. 5 is a combined detailed circuit diagram and truth table illustrating a prior art Booth encoder/selector circuit and signal propagation delays therethrough;

FIG. 6 is a combined detailed circuit diagram and truth table illustrating a further prior art Booth encoder/selector circuit and signal propagation delays therethrough;

FIG. 7 is a combined detailed circuit diagram and truth table illustrating a still further prior art Booth encoder/selector circuit and signal propagation delays therethrough; and

FIG. 8 is a detailed circuit diagram of the encoder/selector circuit of FIGS. 2 and 4 that also shows the signal propagation delays therethrough.

Claims

1. An apparatus, comprising: at least one encoder circuit including a plurality of logic gates operable to convert from radix 2 to radix 4 by receiving a group of bits of a multiplier and producing a set of encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes:a first bit that is true when the associated number is 2,a second bit that is true when the associated number is −2,a third bit that is true when the associated number is either negative or zero, anda fourth bit that is true when the associated number has an absolute value of 1.

2. The apparatus of claim 1, wherein the encoder circuit includes: a first circuit operable to receive three bits of the multiplier, yi, yj, yk and to produce the first bit of the set of encoded bits;a second circuit operable to receive the yi, yj, yk bits and to produce the second bit of the set of encoded bits;a third circuit operable to receive the yi bit and to produce the third bit of the set of encoded bits; anda fourth circuit operable to receive the yj, yk bits and to produce the fourth bit of the set of encoded bits.

3. The apparatus of claim 2, wherein the first circuit includes one or more logic gates that operate in accordance with the following truth table:

4. The apparatus of claim 2, wherein the second circuit includes one or more logic gates that operate in accordance with the following truth table:

5. The apparatus of claim 2, wherein the third circuit includes one or more logic gates that operate in accordance with the following truth table:

6. The apparatus of claim 2, wherein the fourth circuit includes one or more logic gates that operate in accordance with the following truth table:

7. The apparatus of claim 1, further comprising N/2 encoder circuits, where N is a number of bits in the multiplier and each encoder circuit is operable to receive a different group of three bits of the multiplier, except for a last one of the encoders which receives a group of two bits of the multiplier and a null bit.

8. The apparatus of claim 7, wherein: the multiplier includes bits y0, y1, y2, y3, . . . yN-1;a first of the encoders receives bits y0, y1, y2;a second of the encoders receives bits y2, y3, y4; andany further of the encoders receives bits in accordance with the pattern established by the above convention.

9. The apparatus of claim 1, further comprising: a plurality of selector circuits, each operable to: (i) receive the encoded bits from the at least one encoder and a respective group of bits of the multiplicand; and (ii) produce a respective bit of a partial product.

10. The apparatus of claim 9, wherein: each selector circuit is operable to receive a respective group of two bits of the multiplicand, Ai, Aj to produce the respective bit of a partial product; andeach selector circuit includes a plurality of logic gates that are operable to produce an output bit, Si, in accordance with the following Boolean expression: Si=(B1 !AND Aj) !AND (B2 !AND Aj) !AND (B4 !AND (B3 XOR Ai)).

11. An apparatus, comprising: at least one selector circuit operable to: (i) receive respective groups of encoded bits of a multiplier and a respective group of bits of a multiplicand; and (ii) produce a respective bit of a partial product,wherein the encoded bits represent a radix 4 conversion of radix 2 numbers, the radix 4 numbers being a group consisting of −2, −1, 0, 1, 2, and the set of encoded bits includes:a first bit that is true when the associated number is 2,a second bit that is true when the associated number is −2,a third bit that is true when the associated number is either negative or zero, anda fourth bit that is true when the associated number has an absolute value of 1.

12. The apparatus of claim 11, wherein: each selector circuit is operable to receive a respective group of two bits of the multiplicand, Ai, Aj to produce the respective bit of a partial product; andeach selector circuit includes a plurality of logic gates that are operable to produce an output bit, Si, in accordance with the following Boolean expression: Si=(B1 !AND Aj) !AND (B2 !AND Aj) !AND (B4 !AND (B3 XOR Ai)), where Bi are the first, second, third and fourth encoded bits.

13. The apparatus of claim 11, further comprising N selector circuits, where N is a number of bits in the multiplicand and each selector circuit is operable to receive a different group of two bits of the multiplicand, except for a last one of the selector circuits which receives one bit of the multiplicand and a null bit.

14. The apparatus of claim 13, wherein: the multiplicand includes bits A0, A1, A2, A3, . . . AN-1;a first of the selector circuits receives bits A0, A1;a second of the selector circuits receives bits A1, A2;a third of the selector circuits receives bits A2, A3; andany further of the selector circuits receives bits in accordance with the pattern established by the above convention.

15. The apparatus of claim 14, wherein: an aggregate of the output bits Si for a given group of encoded bits is a partial product of a product of the multiplier and the multiplicand; anda sum of the partial products is the product of the multiplier and the multiplicand.

16. A method, comprising: converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2,wherein the set of encoded bits includes:a first bit that is true when the associated number is 2,a second bit that is true when the associated number is −2,a third bit that is true when the associated number is either negative or zero, anda fourth bit that is true when the associated number has an absolute value of 1.

17. The method of claim 16, further comprising producing the first, second, third and fourth bits in accordance with the following truth table:

18. The method of claim 17, further comprising converting respective groups of three bits of the multiplier into the encoded bits, except for a last one of the groups which receives includes two bits of the multiplier and a null bit, wherein: the multiplier includes bits y0, y1, y2, y3, . . . yN-1;a first group of three bits of the multiplier includes y0, y1, y2;a second group of three bits of the multiplier includes y2, y3, y4; andany further groups of three bits of the multiplier includes bits in accordance with the pattern established by the above convention.

19. The method of claim 16, further comprising: receiving a respective group of encoded bits and a respective group of bits of the multiplicand; and producing a respective bit of a partial product.

20. The method of claim 16, further comprising: receiving a respective group of two bits of the multiplicand, Ai, Aj and a respective group of encoded bits, Bi; andproducing a bit, Si, of a partial product in accordance with the following Boolean expression: Si=(B1 !AND Aj) !AND (B2 !AND Aj) !AND (B4 !AND (B3 XOR Ai)).

21. The method of claim 20, wherein: the multiplicand includes bits A0, A1, A2, A3, . . . AN-1;a first group of two bits of the multiplicand consists of bits A0, A1;a second group of two bits of the multiplicand consists of bits A1, A2;a third group of two bits of the multiplicand consists of bits A2, A3; andany further groups of two bits of the multiplicand consists of bits in accordance with the pattern established by the above convention.

22. The method of claim 21, further comprising assembling an aggregate of the bits Si for a given group of encoded bits to produce a partial product of a product of the multiplier and the multiplicand.

23. The method of claim 22, further comprising summing the partial products to produce the product of the multiplier and the multiplicand.