Claims
- 1. An instruction architecture comprising:
an n-bit instruction, wherein n=m×16 with m being an integer greater than or equal to one; an m-bit hierarchical bit field within the n-bit defining a basis instruction type for the n-bit instruction; and an (n-m)-bit field within the n-bit instruction for actual instruction bits.
- 2. The instruction architecture of claim 1 wherein m=1 and the 1-bit hierarchical bit field indicates a distinction between two types of instruction, a first which includes indirect very long instruction word and control instructions, and a second which includes arithmetic and load/store instructions.
- 3. The instruction architecture of claim 1 wherein m=2 and the 2-bit hierarchical bit field indicate a distinction between a first group of pluggable instructions and a second group of three major types of instructions.
- 4. The instruction architecture of claim 3 wherein a first type of pluggable instruction packs two 15-bit instructions into said 30-bit field.
- 5. The instruction architecture of claim 3 wherein a first major type of instruction for said second group comprises indirect very long instruction word and control opcodes.
- 6. The instruction architecture of claim 3 wherein a first major type of instruction for said second group comprises arithmetic opcodes.
- 7. The instruction architecture of claim 3 wherein a first major type of instruction for said second group comprises load/store opcodes.
- 8. The instruction architecture of claim 1 wherein m=2 and the 2-bit hierarchical field distinguishes between a dual 15-bit instruction format and a 30-bit instruction format.
- 9. The instruction architecture of claim 1 further comprising an additional single bit field to differentiate between an array-control processor instruction and instructions for an array of processing elements.
- 10. The instruction architecture of claim 1 further comprising a fixed-in-hardware subset of instructions selected from a full processor complement of operation types to allow many control or scalar-oriented tasks to be coded with the fixed-in hardware subset instructions.
- 11. The instruction architecture of claim 1 wherein m≧2 and sequential execution order of multiple 15-bit instructions packed within the instruction is determined by the position of the 15-bit instructions within the instruction.
- 12. A process for direct translation of a 15-bit compact instruction into a 32-bit format comprising the steps of:
receiving the 15-bit compact instruction; determining from an opcode bit field of the 15-bit compact instruction the functional type of translation required; and utilizing a translation processor to incorporate bits from the compact instruction in translating the 15-bit compact instruction into a 32-bit format.
- 13. The process of claim 12 further comprising the step of:
utilizing a programmer loaded bit to allow data type selection dependent upon the programmer loaded bit.
- 14. The process of claim 13 wherein the programmer loaded bit operates to specify two data types, one for a 32-bit word and the other for a 16-bit half-word.
- 15. The process of claim 12 further comprising the step of:
utilizing a programmer loaded bit or bits to allow groups of registers to be selected dependent upon the programmer loaded bit or bits.
- 16. The process of claim 15 wherein the compact instruction operand register specification bit field contains bits defining an offset from a register base address and the operand register is determined by concatenating said offset with said programmer loaded bit or bits.
- 17. A process for dynamically creating a task specific compacted instruction comprising the steps of:
storing programmer selected 32-bit instructions at specific addresses of a partitioned indirect very long instruction word memory (VIM); utilizing function bits in a compacted instruction to select which partition of the partitioned VIM is to be accessed in creating the compacted instruction; utilizing VIM offset bits in a compacted instruction to generate the address of the selected VIM to read one of the previously stored 32-bit instructions; and combining bit fields from the compacted instruction and the previously stored 32-bit instruction to create the task specific instruction.
- 18. The process of claim 17 wherein said VIM offset bits in the compacted instruction are added to a base register address to generate a VIM address.
- 19. The process of claim 17 wherein said VIM offset bits in the compacted instruction are added to a function specific base register address to generate a VIM address.
- 20. The process of claim 17 wherein said bit fields from the compacted instruction are bit fields that change frequently.
- 21. An indirect very ling instruction work (iVLIW) processor comprising:
a plurality of execution units capable of performing a plurality of distinct operations in parallel; a VLIW memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots; an addressing mechanism using address information contained in compacted instruction format for each of said VIM sections providing access to each memory entry, in its associated VIM section independently for input to a translation mechanism; and a translation mechanism for dynamically translating compacted instructions into uncompacted instructions.
- 22. The processor of claim 21 wherein the compacted instructions are 15-bit instructions and the uncompacted instructions are 32-bit instructions.
- 23. A SIMD machine with an array comprising at least one processing element (PE) and an array control processor, the array control processor comprising:
a scalable hierarchical instruction set memory; and a plurality of instructions comprising the scalable hierarchical instruction set.
- 24. The machine of claim 23 wherein said plurality of instructions have a format in which a bit or bits define a basic hierarchy field indicating basic formats and instruction types and a plurality of remaining bits define an instruction field.
- 25. The machine of claim 23 wherein each of said instructions has 16 bits and the basic hierarchy field contains 1 bit and the instruction field contains 15 bits.
- 26. The machine of claim 23 in which each of said instructions contains 32 bits comprising a 2 bit hierarchy field and two fifteen bit instruction fields packed therein.
- 27. The machine of claim 23 in which each of said instructions contains 48 bits comprising a 3 bit hierarchy field and at least one fifteen bit instruction field and at least one 30 bit instruction field are packed therein.
- 28. The machine of claim 24 wherein the basic hierarchy field contains a bit or bit encoding which indicates a distinction between two types of instructions, a first type which includes encapsulated Very Long Instruction Work (eVLIW) and control instructions and, a second type which includes arithmetic and load/store instructions.
- 29. The machine of claim 24 wherein said plurality of instructions have an additional bit or bit encoding which serves to differentiate between instructions for the array control processor and instructions for at least one PE.
- 30. The machine of claim 29 wherein the execution of the PEs and the array control processor are mutually exclusive.
- 31. A SIMD machine with an array comprising at least one processing element (PE) and an array control processor, the array control processor comprising:
a plurality of execution units capable of performing a plurality of distinct operations in parallel; a VLIW memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots; an addressing mechanism using address information contained in compacted instruction format for each of said VIM sections providing access to each memory entry, in its associated VIM section independently for input to a translation mechanism; and a translation mechanism for dynamically translating compacted instructions into uncompacted instructions.
- 32. The instruction architecture of claim 1 wherein m≧2 and multiple 15-bit instructions are packed within the instruction, and at least two of the 15-bit instructions are executed in parallel.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims the benefit of U.S. Provisional Application Serial No. 60/068,021 entitled “Methods and Apparatus for Scalable Instruction Set Architecture” and filed Dec. 18, 1997.
Provisional Applications (1)
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Number |
Date |
Country |
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60068021 |
Dec 1997 |
US |
Divisions (1)
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Number |
Date |
Country |
Parent |
09215081 |
Dec 1998 |
US |
Child |
09543473 |
Apr 2000 |
US |
Continuations (2)
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Number |
Date |
Country |
Parent |
09969077 |
Sep 2001 |
US |
Child |
10424961 |
Apr 2003 |
US |
Parent |
09543473 |
Apr 2000 |
US |
Child |
09969077 |
Sep 2001 |
US |