Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. Memory may be volatile, which requires a power source to maintain its data, or non-volatile, which does not require an external power source to maintain its data. Volatile memory generally includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory generally includes NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.
Memory devices can be combined together to form a storage volume of a memory system such as a solid state drive (SSD). A solid state drive can include non-volatile memory (e.g., NAND flash memory and NOR flash memory), and/or can include volatile memory (e.g., DRAM and SRAM), among various other types of non-volatile and volatile memory. An SSD can have advantages over hard drives in terms of performance, size, weight, operating temperature range, and power consumption. For example, SSDs can have superior performance when compared to magnetic disk drives due to their lack of moving parts, which may avoid seek time; latency, and other electro-mechanical delays associated with magnetic disk drives.
Memory devices generally include memory cells which are used to store data. A memory cell of a memory device can be programmed to a desired data state. For example, a single level cell (SLC) can be programmed to one of two data states, such as a logic high or binary “1” data state and a logic low or binary “0” data state. Multi-level cells (MLCs) can be programmed to one of more than two data states. For example, some Flash MLC memory cells can be programmed to one of three, four, eight, or sixteen data states, where each of these data states is represented by a respective quantity of electric charge placed on or removed from a charge storage structure (e.g., a floating gate). As such, MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can be programmed to store more than one bit.
When data is transmitted from one location to another there is the possibility that an error may occur. Errors can also occur over time while data is stored in a memory. There are a number of techniques that can be used to encode data so that an error can be detected and/or corrected. Since data is routinely transmitted to and from memory, and stored therein, memory can employ error correction techniques to attempt to correct data associated with the memory. One type of error correction involves a low-density parity-check (LDPC) technique. Unencoded, or “raw,” data can be encoded into code words for transmission and/or storage. The code words can subsequently be decoded to recover the data. However, depending on the nature and extent of errors that occur to the encoded code word during transit and/or storage, a decoder may not be successful in properly decoding the code word. Error correction often involves redundant information, such as parity bits, appended to the data bits. The ratio of data bits to the total number of bits (data bits plus redundant information bits) is the code rate. ECCs with higher code rates often promote better error correction, but increase processing times and can lead to latency problems. Accordingly, efficient use of code rate is of concern when implementing an ECC.
Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.
Embodiments of the present invention will now be described in detail with respect to the several drawings.
The host 102 may be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. The host 102 may include a number of memory access devices (e.g., a number of processors). The host 102 may also be a memory controller, such as where memory system 104 is a memory device (e.g., a memory device having an on-die controller).
The memory system 104 may be a solid state drive (SSD) and may include a host interface 106, a controller 108 (e.g., a processor and/or other control circuitry), and a number of memory devices 110. As used herein, the memory system 104, the controller 108, and/or the memory device 110 may also be separately considered an “apparatus.” The memory 110 may comprise a number of solid state memory devices such as NAND flash devices, which provide a storage volume for the memory system 104.
The controller 108 may be coupled to the host interface 106 and to the memory 110 via a plurality of channels to transfer data between the memory system 104 and the host 102. The interface 106 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the apparatus 100, the interface 106 may be a serial advanced technology attachment (BATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among other connectors and interfaces. In general, interface 106 provides an interface for passing control, address, data, and other signals between the memory system 104 and the host 102 having compatible, receptors for the interface 106.
The controller 108 may communicate with the memory 110 (which in some embodiments can include a number of memory arrays on a single die) to control data read, write, and erase operations, among other operations. The controller 108 may include a discrete memory channel controller for each channel (not shown in
The controller 108 may include an ECC encoder 112 for encoding data bits written to the memory 110. The ECC encoder 112 may include a single panty check (SPC) encoder, and/or an algebraic error correction circuit such as one of the group including a Bose-Chaudhuri-Hocquenghem (BCH) ECC encoder and/or a Reed Solomon ECC encoder, among other types of error correction circuits. An example ECC encoder 112 is discussed in further detail below with respect to
The ECC encoder 112 and the ECC decoder 114 may each be discrete components such as an application specific integrated circuit (ASIC) or the components may reflect functionality provided by circuitry within the controller 108 that does not necessarily have a discrete physical form separate from other portions of the controller 108. Although illustrated as components within the controller 108 in
The memory 110 may include a number of arrays of memory cells (e.g., non-volatile memory cells). The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. Although floating-gate type flash memory cells in a NAND architecture are generally referred to herein, embodiments are not so limited. The cells may be multi-level cells (MLC) such as triple level cells (TLC) which store three data bits per cell. The memory cells can be grouped, for instance, into a number of blocks including a number of physical pages. A number of blocks can be included in a plane of memory cells and an array can include a number of planes. As one example, a memory device may be configured to store 8 KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device.
According to a number of embodiments, controller 108 may be configured to control encoding of a number of received data bits according to the ECC encoder 112 that allows for later identification of erroneous bits and the conversion of those erroneous bits to erasures. The controller 108 may also control programming the encoded number of received data bits to a group of memory cells in memory 110. As described further herein, the manner in which the bits are programmed and encoded may allow for higher code rates during decoding operations and read functions.
In operation 202, erroneous cells are identified. An erroneous cell may be any individual memory cell which has at least one bit in it which is in error. For example, in a TLC memory cell, if one of the three stored bits is in error, then the entire cell is determined to be erroneous and is marked as such. As will be appreciated by those skilled in the art, a number of possible strategies may be used to identify erroneous cells. In one embodiment, the data bits stored in the cells of a memory (e.g., memory 110) may be arranged and encoded to form a tensor product code. The tensor product code may employ constituent codes, such as an SPC code and/or a BCH code which increases the code rate of the ECC. The tensor product code is discussed in further detail below with respect for
In operation 204, the identified erroneous cells are converted to erasures. An erasure is a cell in which all of the bits of the cell are erased from the cell. In practice, the identification of a cell as an erasure is a signal to the ECC decoder (e.g., the ECC decoder 114) that an equal likelihood exists of each bit in the cell being a logical zero or one. That is, the memory does not have any confidence that any particular bit within the erased cell is a zero and not a one or vice versa. By converting errors to erasures, the flash channel of the memory can be converted from an errors only channel, such as a binary symmetric channel (BSC) that requires an associated confidence value for each bit, to an erasures only channel, such as a binary erasure channel (BEC) that does not require an associated confidence value. A BEC has a higher possible code rate than a BSC because the cells which were not marked as erasures are taken to be correct.
In operation 206, the erasures are corrected. In various embodiments, the erasures may be corrected using an LDPC code. Each of the bits in the erased cells has an equal probability of being a zero or a one. The correct value of each of the erased bits may be reconstructed using an LDPC code. For example, as known, an LDPC code may reconstruct a valid code word from a sequence of valid bits. The LDPC code may reconstruct the valid code word by iteratively identifying one erased bit at a time.
The SPC encoder circuit 304 may be any hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof capable of receiving a plurality of bits over a data channel and generating a single parity check bit at regular intervals for the received data. In certain embodiments, a single parity check bit is generated by the SPC encoder circuit 304 for each cell of a memory (e.g., memory 110). For example, in a TLC memory device, the SPC encoder circuit 304 generates a single parity check bit for every three bits in the received data because each cell in a TLC memory stores three bits. As depicted in
The BCH encoder circuit 306 may be any hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof capable of accessing the storage device 308 and encoding data according to a BCH encoding method. As discussed in further detail below with respect to
The storage device 308 may be any data storage device capable of being read from and written to by the SPC encoder circuit 304 and the BCH encoder circuit 306. In various embodiments, the storage device 308 may be one of a cache memory or a register.
In operation 402, the controller fills a first block of cells with data bits. As shown in
In operation 404, the controller generates single parity check bits for the cells in the first block. In various embodiments, the controller generates the single parity check bits using an SPC encoder circuit, such as SPC encoder circuit 304. The controller may add the bits, modulo 2, in each cell and generate a single parity check bit, whose value indicates whether the sum of the bits in the cell is odd or even. For example, if the bits stored in the cell are 010, then the sum of the bits is odd, so the single parity check bit may have a value of 1. Similarly, if the bits stored in the cell are 101, then the sum of the bits is even, and the single parity check bit may have a value of 0. In certain embodiments, the single parity check bits are stored as associated enabling bits in an associated storage device, such as storage device 308, which may be a local cache or register. The embodiment of
In operation 406, the controller generates a plurality of BCH parity bits. The controller may generate the plurality of BCH parity bits using a BCH encoder circuit, such as BCH encoder circuit 306. In various embodiments, the controller generates the BCH parity bits by using the single parity check bits generated in operation 404 as the data to be encoded. The generated BCH parity bits may be stored as associated enabling bits in a local storage device, such as storage device 308, which may be a cache or a register. As shown in
In operation 408, the controller stores the remaining data bits in a second block of cells. As shown in
In operation 410, the controller generates a second set of single parity check bits for the data bits stored in the second block and the BCH parity bits. As shown in
In operation 412, the controller stores each of the second set of single parity check bits in the second block of cells. As discussed above, an open bit was left in each of the cells (e.g., cells 510a-510n) of the second block (e.g., second block 504) when the remaining data bits were stored in the second block of cells (see operation 408). The controller stores the second set of single parity check bits in the open bits in the second block of cells. In various embodiments, the second single parity check bit stored in each cell is the parity check bit representing the sum of the two data bits in that cell and a BCH parity bit. As shown in
The TPC decoder 602 may generally be any decoder circuit, or combination of decoder circuits, capable of identifying erroneous cells in a TPC and converting the erroneous cells to erasures. In various embodiments, the TPC decoder 602 and its components may be implemented as a hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof.
The SPC decoder circuit 604 may be any hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof capable of receiving a plurality of bits over a data channel and generating a single parity check bit at regular intervals for the received data. In certain embodiments, a single parity check bit is generated by the SPC decoder circuit 604 for each cell of a memory (e.g., memory 110). For example, in a TLC memory device, the SPC decoder circuit 604 generates a single parity check bit for every three bits in the received data because each cell in a TLC memory stores three bits. As depicted in
The BCH decoder circuit 606 may be any hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof capable of decoding data according to a BCH encoding method. As discussed in further detail below with respect to
The LDPC decoder circuit 608 may be any hardware circuit, such as an integrated circuit, software application, firmware, or a combination thereof capable of receiving erasures from the BCH decoder circuit 606 and correcting the erasures. For example, an LDPC code may reconstruct a valid code word from a sequence of valid bits and erasures. The LDPC code may then reconstruct the valid code word by iteratively identifying one erased bit at a time.
In operation 702, the controller computes an SPC parity bit for each cell in the memory (e.g., memory 110). In various embodiments, operation 702 may be performed by the SPC decoder circuit 604 as discussed above with respect to FIG. 6. The SPC parity bits may be computed in a similar manner as described above. For example, in a TLC, each cell has three bits stored in it. The three bits may be added together and the SPC parity represents whether the sum of the bits is odd or even (e.g., 0 for even and 1 for odd). The computed parity bits for the cells may constitute a BCH code word which may be decoded using BCH decoding (e.g., a BCH decoder which decodes data encoded using BCH encoder circuit 306).
In operation 704, the controller performs BCH decoding on the computed SPC parity bits. In various embodiments, BCH decoding may be performed by the BCH decoder circuit 606 as discussed above with respect to
In operation 706, the controller identifies erroneous cells. Because each of the parity bits corresponds to a single cell in the memory, if the bits in the BCH code words at the time of encoding and decoding do not match, then the cell corresponding to that bit in the BCH code word is in error. Further, the location of the erroneous cell may be identified by the parity bits because of the one-to-one correspondence between the parity bits and the memory cells (e.g., the first parity corresponds to the first cell, etc.).
In operation 708, the controller marks the erroneous cells as erasures. Marking a cell as an erasure may include assigning a value of a log-likelihood-ratio (LLR) of 0 to each bit in the cell. Accordingly, after operation 708, the cells in memory may all either be cells which can be read with 100% confidence in their accuracy, or passed as erasures to a subsequent circuit or module which can reconstruct the data in the erased cells (e.g., by an LDPC code). Operation 708 may remove all errors from the memory
In operation 710, the controller converts the flash channel of the memory to an erasures only channel from an errors only channel. By identifying the errors and converting the errors to erasures prior to transferring the data to a final decoder circuit (e.g., LDPC decoder circuit 608), the controller can take advantage of a higher capacity erasures only channel. Erasures only channels have higher capacity than errors only channels, which means that a higher code rate is achievable on an erasures only channel than an errors only channel.
In operation 712, the controller performs LDPC decoding to correct the erasures. For example, an LDPC code may reconstruct a valid code word from a sequence of valid bits and erasures by reconstructing one erased bit at a time.
This application is a continuation of U.S. patent application Ser. No. 16/141,708 filed Sep. 25, 2018 and issued as U.S. Pat. No. 10,691,538 on Jun. 23, 2020, which is a continuation of U.S. patent application Ser. No. 14/721,913, filed May 26, 2015 and issued as U.S. Pat. No. 10,120,753 on Nov. 6, 2018. The aforementioned applications, and issued patents, are incorporated by reference herein, in their entirety, and for any purposes.
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20200272539 A1 | Aug 2020 | US |
Number | Date | Country | |
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Parent | 16141708 | Sep 2018 | US |
Child | 16874498 | US | |
Parent | 14721913 | May 2015 | US |
Child | 16141708 | US |