Claims
- 1. A method of fusing a memory storage element including a first tunnel-junction device, said method comprising the steps of:
connecting in series with said memory storage element a control element comprising a second tunnel-junction device, thereby forming a series combination, and applying a suitable current to said series combination, to fuse said first tunnel-junction device of said memory storage element, while protecting said second tunnel-junction device of said control element from fusing.
- 2. The method of claim 1, wherein said suitable current is a predetermined current sufficient for fusing said first tunnel-junction device of said memory storage element.
- 3. The method of claim 1, wherein said suitable current is applied for at least a predetermined time interval.
- 4. The method of claim 1, wherein said second tunnel-junction device has a characteristic fusing threshold voltage, and said protecting step is performed by preventing voltage across said second tunnel-junction device of said control element from exceeding said characteristic fusing threshold voltage.
- 5. The method of claim 4, wherein said fusing-threshold-voltage-preventing is performed by connecting a sense amplifier to said series combination, sensing at least one parameter of a suitable voltage and the current through said series combination, and controlling said current through said series combination to a suitable value in accordance with said parameter sensed.
- 6. The method of claim 5, wherein said suitable voltage sensed is a voltage determined by electrically coupling a reference tunnel-junction device to a current source.
- 7. The method of claim 4, wherein said control element has a control-element cross-sectional area, said memory storage element has a memory-storage-element cross-sectional area, and
said control-element cross-sectional area is made about equal to said memory-storage-element cross-sectional area.
- 8. The method of claim 4, wherein said control element has a control-element cross-sectional area, said memory storage element has a memory-storage-element cross-sectional area, and
said fusing-threshold-voltage-preventing is performed by making said control-element cross-sectional area larger than said memory-storage-element cross-sectional area.
- 9. The method of claim 8, wherein said control-element cross-sectional area is made at least twice said memory-storage-element cross-sectional area.
- 10. The method of claim 4, further comprising the step of providing a reference tunnel-junction device, wherein said fusing-threshold-voltage-preventing is performed by connecting a sense amplifier to said series combination, sensing at least one parameter of a suitable voltage and the current through said reference device, and controlling said current through said series combination to a suitable value in accordance with said parameter sensed.
- 11. The method of claim 10 wherein said reference device is connected in a current-mirror configuration with said series combination of said memory storage element and said control element.
- 12. A method of fusing a memory storage element including a first tunnel-junction device having a first characteristic fusing threshold voltage connected in series combination with a control element comprising a second tunnel-junction device having a second characteristic fusing threshold voltage, said series combination being connected in parallel with a reference element including a third tunnel-junction device having a third characteristic fusing threshold voltage less than or substantially equal to said second characteristic fusing threshold voltage, said method comprising the steps of:
applying a suitable current to said series combination, to fuse said first tunnel-junction device of said memory storage element while sensing at least one parameter of a suitable voltage and the current through said reference element; and controlling said suitable current applied through said series combination to a suitable value in accordance with said parameter sensed, thus protecting said second tunnel-junction device of said control element from fusing, said protecting step being performed by preventing voltage across said second tunnel-junction device of said control element from exceeding said second characteristic fusing threshold voltage.
- 13. A memory storage element made by the fusing method of claim 1.
- 14. A memory cell including a memory storage element made by the fusing method of claim 1.
- 15. A storage device including a multiplicity of memory storage elements made by the fusing method of claim 1.
- 16. An electronic device including a multiplicity of memory storage elements made by the fusing method of claim 1.
- 17. A method of programming a memory having a multiplicity of memory storage elements of which each memory storage element includes a first tunnel-junction device having a first characteristic fusing threshold voltage, said method comprising the steps of:
a) connecting in series with each of said memory storage elements a control element comprising a second tunnel-junction device having a second characteristic fusing threshold voltage, thereby forming a series combination; and b) selectively fusing said first tunnel-junction device of each selected memory storage element by applying a suitable current to said series combination; while c) preventing voltage across said second tunnel-junction device of said control element of each selected memory storage element from exceeding said second characteristic fusing threshold voltage, thus protecting said second tunnel-junction device of said control element of said selected memory storage element from fusing; and d) repeating steps (b) and (c) for each selected memory storage element.
- 18. A storage device including a memory made by the method of claim 17.
- 19. An electronic device including a memory made by the method of claim 17.
- 20. An integrated circuit including a memory made by the method of claim 17.
- 21. The method of claim 17, wherein said fusing-threshold-voltage-preventing is performed by connecting a sense amplifier to said series combination, sensing at least one parameter of a suitable voltage and the current through said series combination, and controlling said suitable current in accordance with said parameter sensed.
- 22. The method of claim 17, further comprising the steps of:
providing a reference element in parallel with said series combination, said reference element including a tunnel-junction device having a third characteristic fusing threshold voltage less than or substantially equal to said second characteristic fusing threshold voltage of said tunnel junction of said control element; and connecting a sense amplifier to said reference element, sensing at least one parameter of a suitable voltage and the current through said reference element, and controlling said suitable current in accordance with said parameter sensed.
- 23. A storage device including a memory made by the method of claim 22.
- 24. An electronic device including a memory made by the method of claim 22.
- 25. An integrated circuit including a memory made by the method of claim 22.
- 26. A memory structure comprising:
a memory storage element, said memory storage element having a memory storage element cross-sectional area; a control element comprising a tunnel-junction device, said control element having a control element cross-sectional area, said control element being electrically coupled to said memory storage element and being configured to control the state of said memory storage element; and a reference element, said reference element being configured as a reference to protect said control element when selectively controlling the state of said memory storage element.
- 27. The memory structure of claim 26, wherein said control element cross-sectional area is larger than said memory storage element cross-sectional area.
- 28. The memory structure of claim 26, wherein said memory storage element comprises a tunnel-junction device.
- 29. The memory structure of claim 26, further comprising first and second electrodes, wherein said control element comprises an oxide of said first electrode.
- 30. The memory structure of claim 29, wherein said control element is disposed between said first and second electrodes.
- 31. The memory structure of claim 26, further comprising first and second electrodes, wherein said memory storage element comprises an oxide of said second electrode.
- 32. The memory structure of claim 26, further comprising first and second electrodes, wherein said control element comprises an oxide of said first electrode, and wherein said memory storage element comprises an oxide of said second electrode.
- 33. The memory structure of claim 26, wherein said memory storage element comprises a tunnel-junction device portion, said memory structure further comprising first, second, and third electrodes, said memory storage element being disposed between said second and third electrodes, wherein said control element comprises an oxide of said first electrode, and wherein said memory storage element tunnel-junction device portion comprises an oxide of said third electrode.
- 34. The memory structure of claim 26, wherein said control element and said memory storage element are substantially co-planar.
- 35. The memory structure of claim 26, wherein said control element and said memory storage element are horizontally separated.
- 36. The memory structure of claim 26, wherein said control element and said memory storage element are vertically separated.
- 37. An integrated circuit including the memory structure of claim 26.
- 38. A memory carrier including the memory structure of claim 26.
- 39. An electronic device configured to receive the memory carrier of claim 38.
- 40. An electronic device including the memory structure of claim 26.
- 41. The memory structure of claim 26, further comprising a current source, said reference element including a tunnel-junction device, said reference element being configured as a reference for said control element in control of said current source when selectively controlling the state of said memory storage element.
- 42. A memory structure comprising:
a first electrode; a second electrode; a third electrode; a memory storage element disposed between said second electrode and said third electrode, said memory storage element having a memory storage element cross-sectional area; a control element disposed between said first electrode and said second electrode, said control element comprising a tunnel-junction device, said control element having a control element cross-sectional area, said control element being electrically coupled to said memory storage element and being configured to control said memory storage element; and a reference element, said reference element being configured as a reference to protect said control element when selectively controlling the state of said memory storage element.
- 43. The memory structure of claim 42, wherein:
said first electrode comprises a first conductor having a top surface; said third electrode comprises a second conductor having a top surface and being disposed horizontally adjacent to said first conductor; said control element is disposed on said top surface of said first conductor; and said memory storage element is disposed on said top surface of said second conductor.
- 44. The memory structure of claim 42, wherein said first conductor and said second conductor are substantially co-planar.
- 45. The memory structure of claim 42, wherein said control element comprises an oxide of said first conductor.
- 46. The memory structure of claim 42, wherein said memory storage element comprises an oxide of said second conductor.
- 47. The memory structure of claim 42, wherein said control element comprises an oxide of said first conductor, and wherein said memory storage element comprises an oxide of said second conductor.
- 48. The memory structure of claim 42, wherein said control element comprises an oxide different from an oxide of said first conductor.
- 49. The memory structure of claim 42, wherein said memory storage element comprises an oxide different from an oxide of said second conductor.
- 50. The memory structure of claim 42, wherein:
said second electrode comprises a conductive tub having a base and a rim, said base and said rim being vertically separated; said first electrode comprises a first memory selection conductor vertically adjacent to said base of said conductive tub; said control element is disposed between said first memory selection conductor and said base of said conductive tub; said third electrode comprises a second memory selection conductor vertically adjacent to a portion of said rim of said conductive tub; and said memory storage element is disposed between said second memory selection conductor and said rim of said conductive tub.
- 51. The memory structure of claim 42, wherein:
said third electrode comprises a truncated conductive cone having a rim edge; said third electrode comprises a conductor adjacent to said rim edge; and said memory storage element is disposed between said rim edge and said conductor.
- 52. The memory structure of claim 42, wherein:
said third electrode comprises a conductive pillar; said second electrode comprises a conductor laterally adjacent to said conductive pillar; and said memory storage element is disposed between said conductive pillar and said conductor.
- 53. The memory structure of claim 52, wherein said conductor comprises a conductive plate laterally adjacent to said conductive pillar.
- 54. The memory structure of claim 52, wherein said conductor comprises a conductive block laterally adjacent to said conductive pillar.
- 55. The memory structure of claim 42, wherein:
said third electrode comprises a conductive tub; said second electrode comprises a conductor laterally adjacent to said conductive tub; and said memory storage element is disposed between said conductive tub and said conductor.
- 56. The memory structure of claim 55, wherein said conductor comprises a conductive plate laterally adjacent to said conductive tub.
- 57. The memory structure of claim 55, wherein said conductor comprises a conductive block laterally adjacent to said conductive tub.
- 58. The memory structure of claim 42, wherein:
said third electrode comprises a conductive structure having a vertical extent; said second electrode comprises a non-horizontal conductive panel laterally adjacent to said conductor, and comprises a horizontal conductive plate connected to said conductive panel; said first electrode comprises a conductor laterally adjacent to said conductive panel; said memory storage element is disposed between an edge of said horizontal plate and said conductive structure; and said control element is disposed between said conductor and said conductive panel.
- 59. The memory structure of claim 58, wherein said conductive structure comprises a conductive pillar.
- 60. The memory structure of claim 58, wherein said conductive structure comprises a conductive tub.
- 61. The memory structure of claim 58, wherein:
said conductor comprises an elongated conductive wall having a vertical extent; said conductive panel is laterally adjacent to said elongated conductive wall; and said control element is disposed between said conductive panel and said elongated conductive wall.
- 62. The memory structure of claim 42, further comprising a reference element electrically coupled to said third electrode to provide a current reference for said control element.
- 63. A memory structure comprising:
a conductive structure having a vertical extent; a first memory storage element and a first control element laterally adjacent to said conductive structure; said first control element comprising a tunnel-junction device, said control element having a cross-sectional area that is larger than a cross-sectional area of said first memory storage element; a second memory storage element and a second control element laterally adjacent to said conductive structure; and said second control element comprising a tunnel-junction device and said second control element having a cross-sectional area that is larger than a cross-sectional area of said second memory storage element.
- 64. The memory structure of claim 63, further comprising:
further conductive structure having a vertical extent vertically adjacent to said conductive pillar; a third memory storage element and a third control element laterally adjacent to said further conductive structure; said third control element comprising a tunnel-junction device, said third control element having a cross-sectional area that is larger than a cross-sectional area of said third memory storage element; a fourth memory storage element and a fourth control element laterally adjacent to said further conductive structure; and said fourth control element comprising a tunnel-junction device, said fourth control element having a cross-sectional area that is larger than a cross-sectional area of said fourth memory storage element.
- 65. A memory structure comprising:
means for storing a memory state; means for controlling said means for storing; said means for controlling including a tunnel-junction device, and said means for controlling having a larger cross-sectional area than said means for storing.
- 66. The memory structure of claim 65, wherein said means for controlling further comprises reference means and means for controlling current responsive to said reference means.
- 67. A memory structure comprising:
a plurality of layers of memory cells; each memory cell comprising a first electrode, a second electrode, a third electrode, a memory storage element disposed between said second electrode and said third electrode, and a control element disposed between said first electrode and said second electrode; and said control element including a tunnel-junction device and having a cross-sectional area that is greater than a cross-sectional area of said memory storage element.
- 68. The memory structure of claim 67 wherein:
said second electrode comprises a conductive tub having a base and a rim that are vertically separated; said first electrode comprises a first memory selection conductor vertically adjacent to said base of said conductive tub; said control element is disposed between said first memory selection conductor and said base of said conductive tub; said third electrode comprises a second memory selection conductor vertically adjacent to a portion of said rim of said conductive tub; and said memory storage element is disposed between said second memory selection conductor and said rim of said conductive tub.
- 69. The memory structure of claim 67 wherein:
said third electrode comprises a conductive pillar; said second electrode comprises a conductor laterally adjacent to said conductive pillar; and said memory storage element is disposed between said conductive pillar and said conductor.
- 70. The memory structure of claim 67 wherein:
said third electrode comprises a conductive tub; said second electrode comprises a conductor laterally adjacent to said conductive tub; and said memory storage element is disposed between said conductive tub and said conductor.
- 71. A memory structure comprising:
a plurality of layers of memory cells; each memory cell comprising means for storing a memory state and means for controlling said means for storing; and said means for controlling including tunnel-junction device means and having a larger cross-sectional area than said means for storing.
- 72. The memory structure of claim 71, further comprising reference means for providing a current reference for said means for controlling said means for storing.
- 73. A method of making a memory structure, said method comprising the steps of:
a) forming a control element of a device type including a tunnel-junction device; b) forming a memory storage element having a cross-sectional area that is smaller than a cross-sectional area of said control element; c) electrically coupling said control element with said memory storage element; d) providing first conductive connections to said memory storage element; and e) providing second conductive connections to said control element, said second conductive connections being adapted to control said control element for controlling said memory storage element.
- 74. A memory structure made in accordance with the method of claim 73.
- 75. A method of making a memory structure, said method comprising the steps of:
creating a first electrode; forming on the first electrode a control element of a device type including a tunnel-junction device; creating a second electrode; and forming a memory storage element having a cross-sectional area that is smaller than a cross-sectional area of said control element.
- 76. The method of claim 75, wherein forming the control element on the first electrode comprises forming an oxide different from an oxide of the first electrode.
- 77. The method of claim 75, wherein forming the memory storage element on the second electrode comprises forming an oxide different from an oxide of the second electrode.
- 78. The method of claim 75, wherein forming the memory storage element comprises forming the memory storage element on a top surface of the first electrode.
- 79. The method of claim 75, wherein forming the control element comprises forming the control element on a top surface of the second electrode.
- 80. The method of claim 75, wherein:
forming the memory storage element comprises forming the memory storage element on a top surface of the first electrode; forming the control element comprises forming the control element on a top surface of the second electrode.
- 81. The method of claim 75, wherein
forming the control element comprises forming the control element on a side surface of the first electrode; creating a second electrode comprises creating a second electrode that is in contact with the control element and laterally adjacent to the first electrode; and forming the memory storage element comprises forming the memory storage element on a side surface of the second electrode.
- 82. The method of claim 75 further including forming a conductive structure having vertical extent in contact with the memory storage element and laterally adjacent to the second electrode.
- 83. The method of claim 75 wherein:
forming the control element comprises forming the control element on a horizontal surface of the first electrode; creating a second electrode comprises forming a conductive tub vertically adjacent to the first electrode, said conductive tub having a base in contact with the control element and said conductive tub having a rim vertically separated from the base; and forming the memory storage element comprises forming the memory storage element on the rim of the conductive tub.
- 84. A memory structure made in accordance with the method of claim 75.
- 85. A method of making a memory structure, said method comprising:
forming in a first memory layer a plurality of memory cells, each memory cell including a memory storage element and a control element including a tunnel-junction device and said control element having a cross-sectional area that is larger than a cross-sectional area of the memory storage element; and forming in a second memory layer a plurality of memory cells, each memory cell including a memory storage element and a control element including a tunnel-junction device and said control element having a cross-sectional area that is larger than a cross-sectional area of the memory storage element.
- 86. The method of claim 85, wherein forming in a first memory layer a plurality of memory cells comprises forming in the first memory layer a plurality of memory tunnel-junction oxide regions and a plurality of control tunnel-junction oxide regions.
- 87. The method of claim 85, further comprising forming a plurality of reference elements, a reference element being formed corresponding to each control element formed.
- 88. The method of claim 87, wherein forming a plurality of reference elements comprises forming a plurality of reference tunnel-junction oxide regions.
- 89. A memory structure made by the method of claim 85.
- 90. A storage device including a memory structure made by the method of claim 85.
- 91. An electronic device including a memory structure made by the method of claim 85.
- 92. An integrated circuit including a memory structure made by the method of claim 85.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of co-pending and commonly assigned application Ser. No. 10/116,497, filed Apr. 2, 2002, the entire disclosure of which is incorporated herein by reference.
Divisions (1)
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Number |
Date |
Country |
Parent |
10236274 |
Sep 2002 |
US |
Child |
10756450 |
Jan 2004 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
10116497 |
Apr 2002 |
US |
Child |
10236274 |
Sep 2002 |
US |