Patent Application
20080180899
Computer systems have a limited number of memory slots. If a user, vendor, or manufacturer wishes to install a lot of memory into a computer system, various problems may arise. For example, installing available memory modules into the limited number of memory slots may not allow sufficient memory to be added to the system. Also, the largest available memory modules tend to use the latest memory technology which usually has a high price premium per bit of memory compared to more mature memory technology.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect, direct, optical or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, or through a wireless electrical connection.
Embodiments provide methods and systems to implement a circuit base having the components of multiple memory modules. For example, multiple sets of memory buffers with associated memory chips can be assembled onto a single circuit base. Each set is treated as a separate memory module and forms part of a daisy chain. In at least some embodiments, clock circuitry and auxiliary power circuitry are provided on the circuit base to ensure clocking and power needs of the multiple sets are met.
Referring now to the drawings and in particular to
As will later be described, the multi-memory module 110 comprises a circuit base having multiple sets of memory buffers with associated memory chips. Each of the sets is treated as a separate memory module and forms part of a daisy chain.
As shown, the multi-memory module 110 can be inserted into an available memory slot 108 (e.g., a DIMM slot) coupled to the host bridge 104. Although DIMM technology is discussed in illustrated embodiments, other memory technologies now known or later developed could alternatively be assembled and used for a multi-memory module.
The computer system 100 also may comprise other components. For example, peripheral components could be supported by 64-bit Peripheral Component Interconnect (PCI) slots 112 coupled to the host bridge 104 or by 32-bit PCI slots 114 coupled between the host bridge 104 and an input/output (I/O) bridge 116 (sometimes referred to as a “South” bridge). The I/O bridge 116 interfaces the host bridge 104 with a variety of components such as Integrated Drive Electronics (IDE) ports 122, a Basic Input/Output System (BIOS) 120, a Super I/O controller 124 and Universal Serial Bus (USB) ports 118. The Super I/O controller 124 provides an interface for keyboard and mouse ports 126, a parallel port (LPT) 128 and a serial port (COM) 130. Again,
In at least some embodiments, standard memory modules (e.g., DIMM modules) 210 or the multi-memory modules 110A, 110B could be inserted into the memory slots 108. The choice to insert standard memory modules 210 and/or certain multi-memory modules 110A, 110B could be based, for example, on space limitations within the chassis 101, memory capacity needs, the number of memory slots 108, cost considerations, motherboard layout, cooling arrangements or other factors.
The system 200 also comprises a power supply 204 that supplies power to the memory slots 108 on the motherboard 202. In at least some embodiments, power from the power supply 204 is regulated by a voltage regulator (VR) 208 on the motherboard 202 prior to being passed to standard memory modules 210 and/or the multi-memory modules 110A, 110B via the memory slots 108. To help with the discussion of powering multi-memory modules, any power received via the memory slots 108 is hereinafter referred to as “slot power.” Because multi-memory modules 110A, 110B have more components than a standard memory module 210, the slot power may be insufficient for powering multi-memory modules 110A, 110B. Thus, in at least some embodiments, auxiliary power is provided to the multi-memory modules 110A, 110B from the power supply 204. The auxiliary power can be provided to each multi-memory module 110A, 110B via an auxiliary connection which is separate from the memory slot connections. For example, at least one of the multi-memory modules 110A, 110B may have power circuitry that receives the auxiliary power and regulates the power for use by components of the multi-memory modules 110A, 110B.
As an example, if multi-memory module 110A has two sets of memory buffers and associated memory chips and multi-memory module 110B has four sets of memory buffers and associated memory chips, then multi-memory module 110B may receive auxiliary power while multi-memory module 110A does not. In some embodiments, the auxiliary power is combined with the slot power to power some or all of the components of the multi-memory module 110B. Additionally or alternatively, the slot power is provided to certain components of the multi-memory module 110B while the auxiliary power is provided to other components.
As shown, the system 200 also comprises a fan 206 or other cooling mechanism within the chassis 201. The fan 206 can be placed above the multi-memory modules 110A, 110B or to the side of the multi-memory modules 110A, 110B and functions to move heat away from the multi-memory modules 110A, 110B or other components inside the chassis 201. In at least some embodiments, the installation of multi-memory modules 110A, 110B in the memory slots 108 functions to increase or maintain a cooling effect of the fan 206 on memory installed in the system 200. As an example, one or two multi-memory modules could be used instead of four standard memory modules 210 to increase a cooling effect of the fan 206. If one multi-memory module replaces four standard memory modules 210, the multi-memory module could potentially be placed more directly in the air flow of the fan 206 than could the four standard memory modules. Also, one or two multi-memory modules could be spaced farther apart in the system 200 than could four standard memory modules 210. Again, fillers could be inserted into empty memory slots 108 as needed.
Installing multi-memory modules 110A, 110B instead of standard memory modules 210 in the system 200 can also reduce system costs. As new generations of memory are introduced by manufacturers, the memory is denser than in previous generations of memory. This new, denser memory is typically more expensive per bit of memory. Therefore, if desired memory capacity for a system can be achieved using less dense and less expensive memory, system costs will be reduced. Multi-memory modules make this possible. As an example, a 4 GB standard DIMM could be manufactured using 512 MB memory chips. In contrast, a 4 GB multi-DIMM could be manufactured using 128 MB memory chips. The comparative cost of using 512 MB memory chips (in the standard DIMM) versus 128 MB memory chips (in the multi-DIMM) could enable a 4 GB multi-DIMM to be less expensive than a 4 GB standard DIMM.
The multi-memory module components are organized into sets 302A-302D. Set 302A comprises Advanced Memory Buffer (AMB) 306A and associated Dynamic Random Access Memory (DRAM) 304A. Set 302B comprises AMB 306B and associated DRAM 304B. Set 302C comprises AMB 306C and associated DRAM 304C. Set 302D comprises AMB 306D and associated DRAM 304D. Each set may have the same memory capacity or a different memory capacity. Also, the number of sets on the multi-memory module 110 may vary. In at least some embodiments, the number of AMBs on the multi-memory module 110 varies according to different memory controllers or different fully-buffered DIMM specifications of a system.
The sets 302A-302D are controlled in daisy chain fashion with communications being “northbound” or “southbound.” As used herein, “northbound” refers to communications directed towards a memory controller (e.g., reads) and “southbound” refers to communications directed away from a memory controller 106 (e.g., writes). As shown, each AMB comprises a “primary northbound port” (PNP), a “secondary northbound port” (SNP), a “primary southbound port” (PSP) and a “secondary southbound port” (SSP). In at least some embodiments, the southernmost AMB on a multi-memory module does not implement either an SNP or an SSP (i.e., there is no memory “south” of a particular AMB on the multi-memory module).
As an example, if the multi-memory module 110 receives commands/data from the memory controller 106, the AMB 306A receives the commands/data via its PSP. The AMB 102A analyzes the commands/data to determine the target. If the AMB 102A is the target, the commands/data are consumed. Otherwise, the AMB 102A forwards the commands/data via its SSP to the AMB 306B. The AMB 306B receives the commands/data via its PSP and the process is repeated until the commands/data reach the target(s). If the multi-memory module 110 is returning data to the memory controller 106, the data can be received via a SNP and forwarded via a PNP of each AMB until the data reaches the memory controller 106. As shown, the southernmost AMB on the multi-memory module 110 (AMB 306D in
In at least some embodiments, an AMB (e.g., the southernmost AMB) selectively routes signals to the additional connector 316 or to the edge connector 312. For example, switching logic 318 may enable a user to select whether signals are routed between the southernmost AMB and the additional connector 316 or between the southernmost AMB and the edge connector 312. In some embodiments, the switching logic 318 automatically detects if a valid module is inserted into the additional connector 316 and responds by routing signals between the southernmost AMB and the additional connector 316 rather than to the edge connector 312. If a valid module is not inserted into the additional connector 316, the switching logic 318 routes signals between the southernmost AMB and the edge connector 312.
In at least some embodiments, not all AMBs on the multi-memory module 110 need to be loaded. For example, at least one AMB and its associated DRAM may be “no-loaded” as long as the set resides at the secondary bus end. Thus, the secondary bus will not be routed to the edge connector 312 nor to the additional connector 316 and any partially loaded multi-memory module effectively ends the memory channel (i.e., no memory downstream from the no-loaded set will be recognized).
In at least some embodiments, the multi-memory module 110 also comprises clock circuitry 308 mounted on the circuit base 310. The clock circuitry 308 buffers a clock signal received via the edge connector 312 and provides clock signals to the various components of the multi-memory module 110.
In at least some embodiments, the multi-memory module 110 also comprises voltage regulation (VR) circuitry 314 mounted on the circuit base 310. The VR circuitry 314 regulates auxiliary power provided to the multi-memory module 110. In at least some embodiments, the auxiliary power is received via a connection that is separate from the standard power connection on the edge connector 312 (i.e., the slot power). The auxiliary power can be combined with the slot power to power some or all of the components of the multi-memory module 110. Additionally or alternatively, the slot power is provided to certain components of the multi-memory module 110 while the auxiliary power is provided to other components.
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Other multi-memory module layouts are possible with different layouts potentially affecting the quality of data signals and power signals on each multi-memory module. The different layouts also potentially affect how multi-memory modules connect to each other. For example, the southernmost AMB of a multi-DIMM could be positioned on the left, the top or the right of a given circuit base to facilitate routing to and from the additional connector 316 which could be placed on the top, the left, or the right of the given circuit base. As previously mentioned, the additional connector 316 enables another memory module or multi-memory module to be connected to the multi-memory module 110.
In at least some embodiments, the shape and size of the multi-memory module 110 can vary while maintaining the standard edge connector 312 and a single circuit base. In
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Other multi-memory module shapes are also possible to enable the multi-memory module 110 to avoid contact with known components in a system. Also, a plurality of multi-memory modules having different shapes can be connected (e.g., via an additional connector 316) as needed to provide a desired memory capacity for a system. Also, multi-memory modules may be flexible or semi-flexible to facilitate placement in a system. In at least some embodiments, each multi-memory module or combination of multi-memory modules is prepared according to different system parameters and user requests such as memory controller specifications, chassis size, costs, airflow within chassis, arrangement of internal components, or other parameters.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
