Methods and systems for accessing memory

Abstract

One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are schematic diagrams illustrating a folded bitline ferroelectric memory device having a conventional sense amp and associated circuitry;

FIGS. 2A-2D are schematic diagrams illustrating aspects of one memory device;

FIGS. 2E-2F are timing diagrams relating to the memory device of FIGS. 2A-2D; and

FIG. 3 is flow chart relating to aspects of a method for performing memory operations in one memory device.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. Further, the exemplary implementation can also include features discussed with respect to the prior art system described with reference to FIG. 1A-1B.

One exemplary implementation of the invention is illustrated in FIGS. 2A-2F, in a folded-bitline architecture ferroelectric memory device 200 comprising one or more data cell columns of 512 1T1C ferroelectric (FE) memory cells 218. As shown in FIG. 2A, one exemplary device 200 relates to a 6M ferroelectric memory array that includes a 3M top block 202 and 3M bottom block 204, each of which includes six 512K memory sections 206. Each memory section 206 is further divided into sixteen segments 208 of 32 k each. Each segment may include, for example 512 rows of memory cells (words) and 64 columns (bits) of memory cells. In one embodiment, the segments vertically aligned with one another (e.g., segment (1-1), segment (2-1), . . . , segment (6-1)) may also be referred to as a segment 208A. Although the invention is discussed with reference to this particular memory arrangement, the invention is applicable to ferroelectric memories as well as other types of memories. In other various embodiments, the memory array may be larger or smaller and need not be divided into blocks, sections, or segments, and may include other groupings of memory cells or hierarchies related thereto.

As shown in FIG. 2B, each group of memory cells 210 can share a sensing circuit 212 that is positioned between itself and a group of memory cells in an adjacent section 206. For example, the groups of memory cells 210A and 210B share the sensing circuit 212AB. Similarly, the group of memory cells 210C and the group of memory cells in Col. 1, Section 3, Segment 1 (not shown), share the sensing circuit 212C. Thus, the sensing circuits 212 associated with even numbered columns are coupled to the bottom of every other section associated with that column of memory cells, whereas sensing circuits 212 associated with odd numbered columns are coupled to the top of every other section associated with that column of memory cells.

Contacts 214 couple local IO lines (e.g., LIO1, LIO1′) to the sensing circuits 212 associated with a given column. The local IO lines are further coupled to a global IO select circuit 216 associated with that column, wherein the global IO select circuit 216 may also be referred to as an LMUX circuit. In one embodiment, the top and bottom blocks 202 have common global IO lines as shown in the FIG. 2B. In other embodiment the top and the bottom blocks could have separate global IO lines, and the local IO lines span the sections within each block In still other embodiments, the columns of each segment within in each section could have a selection circuit associated therewith (e.g., in FIG. 2A, there could be seven rows of selections circuits associated with both the top and bottom blocks).

The global IO select circuits 216 selectively couple the local IO lines (e.g., LIO1, LIO1′) to global IO lines (e.g., GIO1, GIO1′). The global IO lines can be coupled to output buffers or other devices, which can, for example transfer data to and from the memory device relative to another external circuit. In the illustrated embodiment, each global IO line can be coupled to a common column in each and every segment. For example, local IO lines LIO1/LIO1′ from the six 32K segments in the top block 202 can be selectively coupled to global IO lines GIO1/GIO1′, and local IO lines LIO64/LIO64′ can similarly be coupled to the global IO lines GIO64/GIO64′.

Referring now to FIG. 2C, one circuit schematic showing one column of FIG. 2B is illustrated, wherein only a single sensing circuit 212 is shown for purposes of brevity and clarity. The column includes memory cells 218a-218c that are accessed during read, restore, and write operations via the bitlines BL and BL′ using wordline and plateline signals WL1-WL512 and PL1-PL512, respectively, wherein the wordlines enable transistors 220a-220c thereby allowing access to the associated memory cells. The FE capacitors in odd numbered data words, such as C_FE1 may be connected to the bitline BL via WL1 and PL1, and the FE capacitors in even numbered data words, such as C_FE2 may be connected to the bitline BL′ via WL2 and PL2.

While one data cell bitline is accessed (e.g., BL1′), a reference voltage generator 222 applies a reference voltage V_REF to the other data cell column bitline (e.g., BL1) by using a transistor 222a or 222b via reference wordline signals RWL_ODD or RWL_EVEN. The bitlines BL and BL′ are precharged or equalized during various memory access operations to a bitline reference voltage BLR, such as VSS or ground, via a bitline equalization circuit 223 using transistors 223a and 223b according to a signal EQ1.

A sensing circuit 212 is coupled to the cell bitlines, wherein the sensing circuit 212 facilitates transferring data between the memory cell bitlines BL′/BL and the local IO lines LIO′/LIO. More specifically, the memory cell bitlines BL/BL′ and sense amp bitline pairs SABL/SABL′ are coupled to one another via transistors 224a and 224b, respectively, of a sense amp connect circuit 224 using a signal TGS1. A cross-coupled latch sense amp 226 comprises sense amp bitlines or terminals SABL and SABL′, and is enabled using sense amp enable signals SE and SE′. Although illustrated and described herein using the exemplary cross-coupled sense amp 226, the invention finds utility in association with any type of sense amp. During read and write operations, the sense amp bitlines SABL and SABL′ are precharged to VSS via transistors 228a and 228b of a sense amp precharge circuit 228, which are controlled with a signal PRC. The sense amp bitline terminals SABL and SABL′ are coupled to local IO bitlines LIO and LIO′, respectively, via transistors 230a and 230b of local IO select circuit 230.

A global IO select circuit 232 is coupled to the local IO lines and can selectively couple the local IO lines LIO/LIO′ to global IO lines GIO/GIO′ to thereby transfer data between the local IO lines and the global IO lines. The global IO select circuit 232 can be configured to selectively bias adjacent local IO lines during a read operation to act as a shield thereby reducing data signal degradation. For example, during a read operation, the global IO select circuit 232 can be configured to inactivate one local IO line (LIO′), and to provide data on the other local IO line (LIO). During a write operation, the global IO select circuit 232 can be configured to provide data on one local IO line while providing complimentary data on the complimentary local IO line. During the write operation, this data and complimentary data on local IO (LIO) lines can be transferred from a global IO line and or complimentary global IO line, respectively. Although FIG. 2C shows a pair of GIO lines associated with each column, it is not necessary to have complimentary GIO lines. For example, a single GIO line can be used to transfer data to a pair of complimentary LIO lines while writing and a single GIO line can receive the data from a LIO line to transfer it to the other circuits. In another embodiment, separate signals GIOPRCZ and GIOPRCZ′ (not shown) can be applied to the gates of the transistors 236b and 236a, respectively which could allow GIO′ to be biased at VDD and act as shield between the GIO lines when the data is transferred from the LIO lines to the GIO lines.

In one embodiment, the global IO select circuit 232 includes a local pre-charge circuit 234 comprising p-channel transistors 234a and 234b, wherein transistor 234a is controlled by signal LIOPRCZ and transistor 234b is controlled by signal LIOWR. During a read access, the local pre-charge circuit 234 pre-charges local IO lines LIO/LIO′ to VDD, after which the signal LIOPRCZ is de-asserted and the signal LIOS is asserted to couple the local IO line LIO to the sense amp bit lines SABL via the transistor 230a. Because the signal LIOS′ is not activated, the SABL′ is not coupled to the LIO′. The LIO′ is held at VDD since the LIOWR (LIO write enable) is low during a read access. In addition, the illustrated global IO circuit 232 includes a global pre-charge circuit 236 comprising p-channel transistors 236a and 236b, wherein the transistors 236a and 236b are controlled by signal GIOPRCZ.

The illustrated global IO select circuit 232 further includes a first coupling circuit 238 that facilitates selective coupling of the local IO lines to the global IO lines. During write memory operations, the first coupling circuit can transfer data between the local and global IO lines, for example, by a pair of CMOS transfer gates 238a and 238b, each of which comprises a PMOS transistor in parallel with an NMOS transistor that are controlled by signals LIOWRZ and LIOWR. Thus, during write memory operations, the first coupling circuit 238 can transfer complimentary data from the complimentary Global IO line GIO′ to the complimentary Local bit line LIO′ while simultaneously transferring data from the Global IO line GIO to the Local IO line LIO.

During read operations, a transfer circuit 240 transfers data from one local IO line (e.g., LIO) to its associated global IO line (e.g., GIO), while the first coupling circuit 238 is disabled. In the illustrated embodiment, the transfer circuit 240 includes a switched power inverter 240a and an n-channel transistor 240b that are controlled by signal LIORDPWRZ, wherein the output signal of the switched power inverter is coupled to the gate of another n-channel transistor 240c. FIG. 2D shows a more detailed schematic in which the switched power inverter 240a comprises a pair of p-channel MOSFETS 240d, 240e and an n-channel MOSFET 240f in series.

Referring now to FIGS. 2E-2F, the functionality of the memory device 200 of FIG. 2C is discussed with respect to illustrative timing diagrams. As discussed further herein, FIG. 2E relates to an illustrative read operation and FIG. 2F relates to an illustrative write operation.

As shown in the read operation of FIG. 2E, at point “A” the LIOPRCZ and GIOPRCZ (“pre-charge” signals) are low, thereby enabling the p-channel transistors of the local IO pre-charge circuit 234 and global IO pre-charge circuit 236. Thus, the local IO lines (LIO, LIO′) and global IO lines (GIO, GIO′) are driven to a high voltage.

At point “B” the LIOPRCZ and GIOPRCZ signals transition to a high voltage, thereby disabling the p-channel transistors 234a, 236a, 236b.

At point “A the TGS1 signal is asserted, and the bitlines BL/BL′ are coupled to SABL/SABL′ by the circuit 224. Transfer of the signal from the data cell to the BL and the reference voltage to BL′ were accomplished prior to the point “B” but not shown. At point “C” the TGS1 is de-asserted to decouple the BL/BL′ from SABL/SABL′ and the signal SE/SE′ are asserted to enable the sense-amp to differentiate the signal on SABL/SABL′ and latch it. However, the sense-amp, the local IO lines LIO/LIO′, and the global IO lines are all electrically isolated from one another. This electrical isolation occurs because transistors associated with local IO select circuit 230, first coupling circuit 238, and transfer circuit 240 are disabled. Because of the pre-charging, at least the local IO lines LIO/LIO′ and global IO lines GIO/GIO′ have electrical charged stored thereon, and are thus shown as having a high voltage at this point. At point “D” the TGS1 is asserted again.

At point “E”, the LIOS signal transitions to a high voltage, enabling transistor 230a of the local IO select circuit 230 and thereby coupling the sense amp terminal SABL to the local IO line LIO. In the exemplary device in order to save power the transistor 230b is not activated so that it will be not draw any current from LIO′ which is coupled to VDD. Thus, charge is transferred from the sense amp terminals to the local IO lines. As illustrated, the voltage on LIO can represent either a “1” or a “0” data value, depending on the value that was stored in the memory cell (and which is latched at the SABL node). While LIO has a data value of either “0” or “1”, a high voltage of approximately VDD is applied to LIO′ throughout the memory access. This high voltage occurs on LIO′ because the LIOWR signal is held low during the read operation, which enables p-channel transistor 234b, thereby coupling LIO′ to VDD throughout the read operation.

At point “F”, the LIORDPWRZ signal transitions low, enabling the transfer circuit 240 and selectively passing the data from LIO to GIO. Thus, during a read operation, the first coupling circuit 238 remains disabled, and does not couple the local IO lines to the global IO lines. At point G the LIORDPWRZ signal transitions high to disable the switched power inverter and transistor 240c. Meanwhile, the transferred data on the GIO is captured by another circuit (not shown). At point “H”, the LIOPRCZ and GIOPRCZ signals have been driven low, and the local IO lines and global IO lines have been pre-charged for another memory access.

As shown in the write operation of FIG. 2F, at point “I” the LIOPRCZ and GIOPRCZ (“pre-charge” signals) are low, again thereby enabling the p-channel transistors of the local IO pre-charge circuit 234 and global IO pre-charge circuit 236 and providing a high voltage on the local IO lines (LIO, LIO1′) and global IO lines (GIO, GIO′).

At point “J” the LIOPRCZ and GIOPRCZ signals transition to a high voltage, thereby disabling the p-channel transistors 234a, 236a, 236b. At this point the bitlines BL/BL′, the local IO lines LIO/LIO′, and the global IO lines are all electrically isolated from one another.

At point “K”, data is provided onto the global IO lines to be written into the memory cell.

At point “L”, the LIOWR and LIOWRZ signals transition to a high voltage and low voltage, respectively. These transitions disable the p-ch transistor 234b and couple the local IO lines to the global IO lines via the first coupling circuit 238, for example via the pass transistors 238a and 238b. Thus, at point “L”, charge passes from the global IO lines to the local IO lines, causing a voltage to develop on the local IO lines.

In the exemplary device in the write cycle the bit cells are interrogated and voltage developed on the bitlines similar to a read cycle. At point “M” the SE signal transitions to a high voltage and SE′ signal transitions to low voltage. The sense-amp read the signal on the bitlines. However, the read signal in the sense-amp is overwritten by the new data as explained below.

At point “N”, the LIOS and LIOS′ signals are asserted, enabling transistors 230a, 230b of the local IO select circuit 230 and thereby coupling the sense amp terminals SABL/SABL′ to the local IO lines LIO/LIO′, respectively. The n-ch 230a and 230b transistors typically allow only VDD-Vt to pass for high side and 0V for low side from LIO/LIO′ to SABL/SABL′. However, the re-generative nature of the latch sense-amp pulls the SABL/SABL′ node to VDD and 0V. The LIOS and LIOS′ are disabled at point N2 The TGS1 signal which is already asserted at this time, allows the 224 coupling circuit to couple the sense-amp terminals to a selected memory cell via the bitlines. Since the n-ch 224 transistors can pass only VDD-Vt (assuming the ON gate voltage of TGS1 is VDD) from the sense-amp terminals (SABL/SABL′) to the bitlines, a p-ch pull up circuit (not shown) coupled to the bitlines may be used to boost the bitline voltage to full VDD.

Lastly, at point “O”, the LIOPRCZ and GIOPRCZ signals have been driven low, and the local IO lines and global IO lines have been pre-charged for another memory access.

In the exemplary device complimentary data is applied to the complimentary GIO lines during write cycle. However, in another embodiment, only single GIO line per data path could be used. The data could be switched to complimentary form at the GIO to LIO interface. For example if the data is 1 at a GIO line then the data impressed (circuit not shown) on LIO would be 1 and on LIO′ it would be 0. Similarly if the data on the GIO line is 0, then the data impressed on LIO would be 0 and on the LIO′ it would be 1.

In another embodiment the signal LIOS′ could also be asserted during read cycle along with the signal LIOS. This may cause the some current to flow from the LIO′ to the sense-amp but would eliminate the need for the LIOS′ signal.

Yet in another embodiment the pre-charge circuit coupled to the LIO′ could also be de-asserted during the read operation similar to that for the LIO and the signal that is developed on LIO′ is discarded and the signal that is developed on the LIO is used to transfer the data on to the global IO line or global IO lines, irrespective of the state of the signal LIOS′ when the LIOS is asserted during the read.

In the exemplary device 1T1C cell configuration is described. However, the invention is also applicable to a 2T2C configuration.

FIG. 3 shows a flow chart for one method 300 that relates to various embodiments of the present invention. Notably, while the methods illustrated herein are illustrated and described as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the operation of memory device which are illustrated and described herein (e.g., memory device 200 in FIG. 2) as well as in association with other systems not illustrated, wherein all such implementations are contemplated as falling within the scope of the present invention and the appended claims.

In one embodiment, the local IO lines and global IO lines may be fabricated in horizontally parallel metal layers separated by a dielectric layer, wherein the local IO lines and global IO lines run perpendicular to one another within the parallel metal layers. For example, the local IO lines could reside in a metal 4 layer and the global IO lines could reside in a metal 5 layer. Further, although the illustrated embodiments have been described with respect to n-channel or p-channel devices, it will be appreciated that the types of devices could suitable interchanged.

Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

Claims

1. A method for accessing a memory device, comprising: during a read operation in the memory device providing one data value on a local IO line while applying a constant voltage to a complimentary local IO line that is associated with the local IO line; andduring a write operation, providing another data value on the local IO line and providing a complimentary data value on the complimentary local IO line.

2. The method of claim 1, further comprising: during the read operation, selectively transferring the one data value on the local IO line to a global IO line.

3. (canceled)

4. The method of claim 1, wherein during the read operation inactivating the complimentary local IO line comprises: discarding any signal on the complimentary local IO line.

5. The method of claim 1, wherein providing the one data value comprises transferring the data value onto the local IO line via a sense amp.

6. The method of claim 5, wherein during the read operation the sense amp transfers the data value onto the local IO line by coupling the sense amp to the local IO line.

7. The method of claim 5, wherein during the read operation the sense amp transfers the data value on the local IO line by coupling the sense amp to the local IO line while the complimentary local IO line is decoupled from the sense amp.

8. The method of claim 1, wherein the memory device is a ferro-electric memory.

9. A sensing system for a memory device, comprising: a sensing circuit associated with a pair of complimentary local IO lines and a memory cell, wherein the sensing circuit comprises a local IO select circuit that facilitates data transfer between the pair of complimentary local IO lines and the memory cell; anda global IO select circuit coupled to the pair of complimentary local IO lines and at least one global IO line, the global IO select circuit operable to selectively transfer data from the at least one global IO line to the complimentary local IO lines;wherein the sensing system is configured to selectively inactivate one of the pair of complimentary local IO lines during a read operation.

10. The system of claim 9, wherein inactivating one of the pair of complimentary local IO lines comprises holding the one of the complimentary local IO lines at a constant voltage during the transfer of data between the one of the complimentary local IO lines and a corresponding global IO line.

11. The system of claim 10, wherein inactivating one of the pair of complimentary local IO lines comprises discarding any signal on the one of the complimentary local IO lines during the transfer of data between the one of the complimentary local IO lines and a corresponding global IO line.

12. The system of claim 9, wherein the memory device is a ferro-electric memory.

13. The system of claim 9, further comprising: a sense amp connection circuit coupled to the memory cell and the sensing circuit, the sense amp connection circuit configured to selectively couple the sensing circuit to the memory cell.

14. The system of claim 9, wherein the global IO select circuit is coupled to more than one sensing circuit via the one of the complimentary local IO lines.

15. A method for accessing memory comprising: during a write operation: providing complementary data to first and second global IO lines, respectively, and transferring the complementary data to first and second local IO lines. respectively, via a first coupling circuit; andduring a read operation: transferring a data value from the first local IO line to the first global IO line via a transfer circuit while holding at least one of: the second global IO line and the second local IO line at an approximately constant voltage.

16. (canceled)

17. (canceled)

18. The method of claim 15, wherein the first and second local IO lines and the first and second global IO lines are associated with a plurality of memory cells.

19. The method of claim 18, further comprising: during the read operation coupling a sensing circuit to the first local IO line to transfer the data.

20. The method of claim 19, further comprising: during the read operation and prior to coupling the sensing circuit to the first local IO line, coupling the sensing circuit to one of the plurality of memory cells to provide the data.

21. The method of claim 18, further comprising: during the read operation coupling the sensing circuit to a memory cell to provide the data to the sensing circuit.

22. The method of claim 21, further comprising: during the read operation after coupling the sense circuit to a memory cell to provide the data, transferring the data from the sensing circuit to the local IO line.

23. The method of claim 15, wherein the memory device is a ferro-electric memory.

24. A method for accessing memory comprising: during a write operation: transferring one data value from a first global IO line to first and second local IO lines, wherein the first and second local IO lines comprise a pair of complimentary local IO lines; andduring a read operation: transferring another data value from the first local IO line to the first global IO line while the second local IO line is held at an approximately constant voltage,

25. (canceled)

26. The method of claim 24 wherein the first and second local IO lines and the first global IO line are associated with a plurality of memory cells.

27. The method of claim 26, further comprising: during the read operation, transferring the one data value from a sensing circuit to the first local IO line.

28. The method of claim 27, further comprising: during the read operation and prior to transferring the one data value from the sensing circuit to the first local IO line, coupling the sensing circuit to a memory cell to provide the one data value.

29. The method of claim 24, wherein the memory device is a ferro-electric memory.