Patent Application
20110045740
Aspects of the invention relate generally to processing semiconductor wafers and more particularly to controlling and optimizing wafer nanotopography during processing.
Semiconductor wafers are commonly used as substrates in the production of integrated circuit (IC) chips. Chip manufacturers require wafers that have extremely flat and parallel surfaces to ensure that a maximum number of chips can be fabricated from each wafer. After being sliced from an ingot, wafers typically undergo grinding and polishing processes designed to improve certain surface features, such as flatness and parallelism.
Simultaneous double side grinding operates on both sides of a wafer at the same time and produces wafers with highly planarized surfaces. Grinders that perform double side grinding include, for example, those manufactured by Koyo Machine Industries Co., Ltd. These grinders use a wafer-clamping device to hold the semiconductor wafer during grinding. The clamping device typically comprises a pair of hydrostatic pads and a pair of grinding wheels. The pads and wheels are oriented in opposed relation to hold the wafer therebetween in a vertical orientation. The hydrostatic pads beneficially produce a fluid barrier between the respective pad and wafer surface for holding the wafer without the rigid pads physically contacting the wafer during grinding. This reduces damage to the wafer that may be caused by physical clamping and allows the wafer to move (rotate) tangentially relative to the pad surfaces with less friction. While this grinding process can improve flatness and/or parallelism of the ground wafer surfaces, it can cause degradation of the topology of the wafer surfaces. Specifically, misalignment of the hydrostatic pad and grinding wheel clamping planes are known to cause such degradation. Post-grinding polishing produces a highly reflective, mirrored wafer surface on the ground wafer but does not address topology degradation.
In order to identify and address topology degradation concerns, device and semiconductor material manufacturers consider the nanotopography of the wafer surfaces. For example, Semiconductor Equipment and Materials International (SEMI), a global trade association for the semiconductor industry (SEMI document 3089), defines nanotopography as the deviation of a wafer surface within a spatial wavelength of about 0.2 mm to about 20 mm. This spatial wavelength corresponds very closely to surface features on the nanometer scale for processed semiconductor wafers. Nanotopography measures elevational deviation of one surface of the wafer and does not consider thickness variations of the wafer, as with traditional flatness measurements. Two techniques, light scattering and interferometry, are generally used to measure nanotopography. These techniques use light reflected from a surface of a polished wafer to detect very small surface variations.
Although nanotopography (NT) is not measured until after final polishing, double sided grinding is one process that affects the NT of finished wafers. In particular, NT defects like C-Marks and B-Rings take form during grinding process from misalignment of the hydrostatic pad and grinding wheel clamping planes and may lead to substantial yield losses. Current techniques designed to reduce NT defects caused by misalignment of hydrostatic pad and grinding wheel clamping planes include manually re-aligning the clamping planes. Unfortunately, the dynamics of the grinding operation and the effects of differential wear on the grinding wheels cause the planes to diverge from alignment after relatively few operations. The alignment steps, which are highly time consuming when performed by an operator, must be repeated so often as to make it a commercially impractical way of controlling operation of the grinder. Additionally, current techniques do not inform the operator of the particular adjustments that should be made to the clamping planes. Instead, the operator is merely provided with data describing the surface of the wafer and then uses trial and error to find an alignment that reduces the nanotopography degradation. Accordingly, the manual alignments are inconsistent among operators and often fail to improve wafer nanotopography.
Further, there is usually some lag between the time that undesirable nanotopography features are introduced into a wafer by a double side grinder and the time they are discovered. After double side grinding, the wafer undergoes various downstream processes like edge polishing, double sided polishing, and final polishing as well as measurements for flatness and edge defects before the NT is checked by a nanomapper or the like. Thus, wafer nanotopography is not known near the time that the wafer is removed from the grinder. Instead, nanotopography is only determined by conventional processes after the ground wafer has been polished in a polishing apparatus. As such, undesirable nanotopography features introduced into the wafer by the double side grinder cannot be identified until post-polishing. Moreover, the wafer is not measured until the cassette of wafers is machined. If suboptimal settings of the grinder cause an NT defect, then, it is likely that all the wafers in the cassette will have this defect leading to larger yield loss. In addition to this unavoidable delay in conventional wafer processes, the operator must wait for each cassette to be processed before getting feedback from the measurements. This leads to a considerable amount of down-time. If the next cassette is already ground before receiving the feedback, there is a risk of even more yield loss in the next cassette due to improper grinder settings.
Aspects of the invention permit nanotopography feedback in less time, allowing adjustments that can be made to improve nanotopography to be recognized and implemented with less lag time for improved quality control and/or wafer yield. According to one aspect of the invention, data indicative of a profile of a wafer ground using a double side grinder is used to predict a nanotopography of the ground wafer. A grinding parameter for improving the nanotopography of subsequently ground wafers is determined based on the predicted nanotopography. The operation of the double side grinder is adjusted in accordance with the determined grinding parameters. As such, aspects of the present invention provide improved nanotopography for wafers subsequently ground by the double side grinder. In another aspect, the present invention utilizes warp data to provide the nanotopography feedback. For example, the present invention may use warp data obtained from a warp measurement device generally used in wafer processing. As such, the present invention advantageously provides a cost-effective and convenient method for improving nanotopography.
A computer-implemented method of processing a wafer embodying aspects of the invention uses a double side grinder having at least a pair of grinding wheels. The method includes receiving, at a processor, data obtained by a warp measurement device for measuring warp of a wafer as ground by the double side grinder. The received warp data is indicative of the measured warp. The method also includes predicting a nanotopography of the wafer based on the received warp data and determining a grinding parameter based on the predicted nanotopography of the wafer. According to the method, instructions are provided for adjusting operation of the double side grinder based on the determined grinding parameter.
In another aspect, a computer-implemented method improves nanotopography of a wafer ground by a double side grinder. The computer-implemented method includes receiving, at a processor, data indicative of a profile of a wafer as ground by the double side grinder and predicting a nanotopography of the wafer based on the received data. A determination is made of a grinding parameter as a function of the received data. The method also includes providing feedback to the double side grinder. The feedback includes the determined grinding parameter to adjust operation of the grinder.
A system for processing a semiconductor wafer using a double side grinder having a pair of wheels also embodies aspects of the invention. The system includes a measurement device for measuring data indicative of a profile of the ground wafer, and a processor configured for determining a grinding parameter as a function of the measured data. In the system, at least one of the wheels of the double side grinder is adjusted based on the determined grinding parameter.
Other objects and features will be in part apparent and in part pointed out hereinafter.
Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.
Referring now to the drawings, aspects of the invention permit nanotopography feedback in less time, allowing adjustments that can be made to improve nanotopography to be recognized and implemented with less lag time for improved quality control and/or wafer yield. In
In an alternative embodiment, the system includes a plurality of grinders 101, each grinding a wafer for further processing according to the system of
In the illustrated embodiment of
In one embodiment, the grinder 101 is a double side grinder.
The hydrostatic pads 211 remain stationary during operation while a drive ring, designated generally by reference numeral 241, moves the wafer W in rotation relative to the pads and grinding wheels 209.
Referring again to
Misalignment of clamping planes 271 and 273 may occur during the double side grinding operation and is generally caused by movement of the grinding wheels 209 relative to the hydrostatic pads 211. Referring to
As previously described, misalignment of the clamping planes 271 and 273 causes undesirable nanotopography features as measured by nanotopography measurement device 115. The undesirable nanotopography features may develop due to uneven grinding of the wafers and/or bending of the wafers. Additionally, misalignment of clamping planes 271 and 273 can cause the grinding wheels 209 to wear unevenly, which can further contribute to development of undesirable nanotopography features caused during the grinding of the wafer W. In some instances, wafers can develop undesirable features that cannot be removed by subsequent processing (e.g., polishing). Advantageously, the present invention minimizes the misalignment of the clamping planes. In particular, the grinding wheels 209 are adjusted by the processor 105 based on data obtained from ground wafers by the measurement device 103 rather than waiting until undesirable nanotopography features are detected by nanotopography measurement device 115.
In one embodiment, the measurement device 103 is a warp measurement device 103 configured to interface with the processor 105. As used by semiconductor wafer manufacturers, the warp measurement device 103 obtains (e.g., detects) warp data for a wafer and measures the warp of the wafer based on the warp data. In one embodiment, the warp measurement device 103 includes one or more capacitive sensors for obtaining the warp data. The obtained warp data is indicative of a profile (e.g., wafer shape) of the supported wafer.
For example, the warp measurement device 103 may execute a line scanning process as illustrated by
As illustrated by
In one embodiment, the warp measurement device 103 uses a self mass compensation algorithm to determine the wafer shape for a gravity free state 607. The self mass compensation determines the shape of the wafer as a function of the line scan data sets, wafer density, an elastic constant, the diameter of the wafer, and the positions of the support pins 603. In one embodiment, warp measurement device 103 measures one or more wafer parameters based on the wafer shape. The wafer parameters may include one or more of the following: warp, bow, TTV (total thickness variation), and/or GBIR (global back surface ideal range). Referring to
Referring again to the system illustrated in
In one embodiment, the storage memory 107 may be volatile or nonvolatile media, removable and non-removable media, and/or any available medium that may be accessed by a computer or a collection of computers (not shown). By way of example and not limitation, computer readable media include computer storage media. The computer storage media in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. For example, computer storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store the desired information and that may be accessed by the computer.
In one embodiment, the processor 105 and the storage memory 107 may be incorporated into one or more computing devices. As known to those skilled in the art, computing devices include a combination of the following: a processor 105, one or more computer-readable media, an internal bus system coupling to various components within the computing devices, Input/Output devices, a networking device, and other devices. Exemplary computing devices include one or a combination of the following: a personal computer (PC), a workstation, a digital media player, and any other digital devices. In another embodiment, the processor 105 accesses data stored by storage memory 107 via a network.
In one embodiment, the processor 105 accesses a feedback program for processing the received warp data. The received warp data may include the line scan data sets and/or the determined wafer shape for the ground wafer. In particular, the processor 105 predicts a nanotopography of the wafer based on the received warp data. The nanotopography of the wafer is predicted, rather than actually measured, since when the measurement device 103 measures the wafer, the wafer has not yet undergone polishing. As previously discussed, current nanotopography measuring devices utilize technology which relies on the wafer being measured to be in a polished state. The processor 105 determines one or more grinding parameters based on the predicted nanotopography of the wafer. In one embodiment, the processor 105 determines a shift parameter. The shift parameter is indicative of a magnitude and a direction for moving the pair of grinding wheels 209 in order to reduce nanotopography degradation caused by misalignment of the grinding wheels 209. In another embodiment, the processor 105 additionally or alternatively determines a tilt parameter. The tilt parameter is indicative of an angle for positioning the pair of grinding wheels with respect to a wafer in order to reduce nanotopography degradation caused by misalignment of the grinding wheels 209.
The operation of the grinder 101 is adjusted based on the determined grinding parameters. For example, the grinding wheels may be adjusted as specified by the determined shift and/or tilt parameters. In one embodiment, the grinding wheels 209 are adjusted as a function of the determined shift and/or tilt parameters and of a previously defined compensation amount. In one embodiment, the grinder 101 is configured to receive the determined grinding parameters and adjust one or more components of the grinder 101 as a function of the determined grinding parameters. In another embodiment, the determined grinding parameters are provided to an operator and the operator configures the grinder 101 to adjust one or more components of the grinder 101 as a function of the determined grinding parameters.
Referring to 909-915 as shown in
According to aspects of the invention, processor 105 repeats operations at 909-915 to compute a predicted diametric nanotopography profile for each line scan data set obtained by the measurement device 103. According to the example illustrated by
Referring again to
According to the optimization cycle, the processor 105 determines a preliminary shift direction based on the predicted NT profile in the B-Ring region. Referring to 931, the processor 105 determines whether the predicted NT profile in the B-Ring region has a valley followed by a peak (referred to as a “VP profile”). If the predicted NT profile is determined to have a valley followed by a peak in the B-Ring region, the preliminary shift direction of the grinding wheels 209 is right. Referring to 933, the processor 105 similarly determines whether the predicted NT profile in the B-Ring region has a peak followed by a valley (referred to as a “PV profile”). If the predicted NT profile is determined to have a peak followed by a valley in the B-Ring region, the preliminary shift direction of the grinding wheels 209 is left.
After determining the preliminary shift direction, the processor 105 determines the shift magnitude based on the B-Ring value. At 941, the processor 105 determines whether the wafer is the first wafer in the optimization cycle. If the wafer is determined to be the first wafer in an optimization cycle, the processor 105 determines the shift magnitude used for grinding the next wafer ground by the grinder (i.e., the second wafer) based on predefined guidelines. In one embodiment, the pre-defined guidelines include a plurality of B-Ring value ranges, each of which are associated with a particular shift magnitude value. The particular shift magnitude value is selected to improve the nanotopograhy of wafers subsequently ground by the grinder 101. According to the illustrated method, at 943 the processor 105 determines whether the B-Ring value is greater than 18 nm. If the B-Ring value is determined to be greater than 18 nm, the shift magnitude is 15 μm and the shift direction is the determined preliminary shift direction. At 944 the processor 105 determines whether the B-Ring value is greater than 8 nm but less than or equal to 18 nm. If the B-Ring value is determined to be greater than 8 nm but less than or equal to 18 nm, the shift magnitude is 10 μm and the shift direction is the determined preliminary shift direction. At 944 the processor 105 determines whether the B-Ring value is greater than 8 nm but less than or equal to 18 nm. If the B-Ring value is determined to be greater than or equal to 5 nm but less than or equal to 8 nm, the shift magnitude is 1 μm and the shift direction is the determined preliminary shift direction.
If the processor 105 determines at 941 that the wafer is not the first wafer in the optimization cycle, the processor 105 executes at 951 an optimization program to determine the shift parameter used for grinding the next wafer. In particular, the number (n) of the wafer in the optimization cycle is identified and the shift parameter for the next wafer (n+1) is determined as a function of the B-Ring values and corresponding shift parameter values for n wafers. In one embodiment, the B-ring values and corresponding shift parameters for the n wafers are fitted using a polynomial fit of degree (n−1). The shift parameter determined using the nth wafer corresponds to a value of the polynomial when the B-Ring value is equal to zero.
As illustrated, processing according to an exemplary method embodying aspects of the invention returns to 903 after the shift parameter is determined at 943, 945, 947, or 951. Likewise, the optimization cycle ends and the method returns to 903 if the processor 105 determines that no adjustment to the grinder 101 is necessary at 925. At 903, the grinder 101 grinds the next wafer according to the determined grinding parameters (e.g., determined shift parameter). At 905, the processor 105 determines whether the next wafer is the first wafer. Since the next wafer is not the first wafer, the processor 105 determines at 961 whether one or more the of follow conditions is true: the B-Ring of the previous wafer is greater than a pre-determined value (e.g., 8 nm); the cassette number is two more than the cassette for which wafers were last measured by the measurement device 103. If one or more of the conditions are true the measurement device 103 obtains warp data for the wafer at 907 at the method proceeds as discussed above. If neither of the conditions is true, the wafer subsequent steps of the illustrated method are not performed for the wafer and the method returns to step 903 for grinding a subsequent wafer.
When introducing elements of the present invention or the preferred embodiment(s) thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
As various changes could be made in the above without departing from the scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.
This application is a divisional of co-pending U.S. patent application Ser. No. 11/967,743, which is a continuation-in-part of U.S. patent application Ser. No. 11/617,430 (now U.S. Pat. No. 7,662,023) filed Dec. 28, 2006, and of U.S. patent application Ser. No. 11/617,433 (now U.S. Pat. No. 7,601,049) filed Dec. 28, 2006, both of which claim the benefit of U.S. Provisional Application No. 60/763,456, filed Jan. 30, 2006, the entire disclosures of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60763456 | Jan 2006 | US | |
| 60763456 | Jan 2006 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11967743 | Dec 2007 | US |
| Child | 12891357 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11617430 | Dec 2006 | US |
| Child | 11967743 | US | |
| Parent | 11617433 | Dec 2006 | US |
| Child | 11617430 | US |
