Patent Grant
8225239
A push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The chip area reduction provides an economic benefit for migrating to newer technologies. The 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%. The reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers.
In the evolution of lithography, as the minimum feature size approached the wavelength of the light source used to expose the feature shapes, unintended interactions occurred between neighboring features. Today minimum feature sizes are being reduced below 45 nm (nanometers), while the wavelength of the light source used in the photolithography process remains at 193 nm. The difference between the minimum feature size and the wavelength of light used in the photolithography process is defined as the lithographic gap. As the lithographic gap grows, the resolution capability of the lithographic process decreases.
An interference pattern occurs as each shape on the mask interacts with the light. The interference patterns from neighboring shapes can create constructive or destructive interference. In the case of constructive interference, unwanted shapes may be inadvertently created. In the case of destructive interference, desired shapes may be inadvertently removed. In either case, a particular shape is printed in a different manner than intended, possibly causing a device failure. Correction methodologies, such as optical proximity correction (OPC), attempt to predict the impact from neighboring shapes and modify the mask such that the printed shape is fabricated as desired. However, the quality of the light interaction prediction is declining as process geometries shrink and as the light interactions become more complex.
In view of the foregoing, solutions are sought for improvements in circuit design and layout that can improve management of lithograpbic gap issues as technology continues to progress toward smaller semiconductor device features sizes.
In one embodiment, a method is disclosed for using sub-resolution shapes placed on a virtual grate to reinforce regular layout shapes in a lithographic process. The method includes determining whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape to be reinforced, is large enough to support placement of a sub-resolution shape. The regular layout shape to be reinforced is placed in accordance with a virtual grate. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the method includes placing the sub-resolution shape so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space.
In one embodiment, a computer readable storage medium having programming instructions stored thereon for generating a semiconductor chip layout recorded in a digital format is disclosed. The computer readable medium includes program instructions for determining whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape to be reinforced, is large enough to support placement of a sub-resolution shape. The regular layout shape to be reinforced is placed in accordance with a virtual grate. The computer readable medium also includes program instructions for placing the sub-resolution shape so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space, upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape.
In one embodiment, a method is disclosed for placing sub-resolution shapes within a layout based on regular layout shape edges. In the method, a first edge of a first regular layout shape to be reinforced is selected. A determination is made that a second regular layout shape is placed parallel to and facing the first edge of the first regular layout shape. A second edge of the second regular layout shape to be reinforced is selected. The second edge faces the first edge. The method also includes determination of a first window of lithographic reinforcement for the first edge, and determination of a second window of lithographic reinforcement for the second edge. The method further includes determining that the first and second windows of lithographic reinforcement support placement of at least one sub-resolution shape within an unoccupied layout space between the first and second edges Then, one or more sub-resolution shapes are placed within the unoccupied layout space such that each of the one or more sub-resolution shapes is placed within at least one of the first and second windows of lithographic reinforcement, and such that the one or more sub-resolution shapes are placed so as to extend parallel to the first and second edges.
In one embodiment, a computer readable storage medium having programming instructions stored thereon for generating a semiconductor chip layout recorded in a digital format is disclosed. The computer readable medium includes program instructions for selecting a first edge of a first regular layout shape to be reinforced. Program instructions are included for determining that a second regular layout shape is placed parallel to and facing the first edge of the first regular layout shape. Program instructions are included for selecting a second edge of the second regular layout shape to be reinforced. The second edge faces the first edge. Program instructions are included for determining a first window of lithographic reinforcement for the first edge, and for determining a second window of lithographic reinforcement for the second edge. Program instructions are included for determining that the first and second windows of lithographic reinforcement support placement of at least one sub-resolution shape within an unoccupied layout space between the first and second edges. Program instructions are included for placing one or more sub-resolution shapes within the unoccupied layout space, such that each of the one or more sub-resolution shapes is placed within at least one of the first and second windows of lithographic reinforcement, and such that the one or more sub-resolution shapes are placed so as to extend parallel to the first and second edges.
Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
Dynamic Array Architecture
The dynamic array architecture represents a semiconductor device design paradigm in which linear-shaped layout features are defined along a regular-spaced virtual grate (or regular-spaced virtual grid) in a number of levels of a cell, i.e., in a number of levels of a semiconductor chip. The virtual grate is defined by a set of equally spaced, parallel virtual lines extending across a given level in a given chip area. The virtual grid is defined by a first set of equally spaced, parallel virtual lines extending across a given level in a given chip area in a first direction, and by a second set of equally spaced, parallel virtual lines extending across the given level in the given chip area in a second direction, where the second direction is perpendicular to the first direction. In one embodiment, the virtual grate of a given level is oriented to be substantially perpendicular to the virtual grate of an adjacent level. However, in other embodiments, the virtual grate of a given level is oriented to be either perpendicular or parallel to the virtual grate of an adjacent level.
In one embodiment, each linear-shaped layout feature of a given level is substantially centered upon one of the virtual lines of the virtual grate associated with the given level. A linear-shaped layout feature is considered to be substantially centered upon a particular line of a virtual grate when a deviation in alignment between of the centerline of the linear-shaped layout feature and the particular line of the virtual grate is sufficiently small so as to not reduce a manufacturing process window from what would be achievable with a true alignment between of the centerline of the linear-shaped layout feature and the line of the virtual grate.
In one embodiment, the above-mentioned manufacturing process window is defined by a lithographic domain of focus and exposure that yields an acceptable fidelity of the layout feature. In one embodiment, the fidelity of a layout feature is defined by a characteristic dimension of the layout feature. Also, it should be understood that the centerline of a given linear-shaped layout feature is defined as a virtual line that passes through the cross-sectional centroid of the linear-shaped layout feature at all points along its length, wherein the cross-sectional centroid of the linear-shaped layout feature at any given point along its length is the centroid of its vertical cross-section area at the given point.
In another embodiment, some linear-shaped layout features in a given level may not be centered upon a virtual line of the virtual grate associated with the given level. However, in this embodiment, the linear-shaped layout features remain parallel to the virtual lines of the virtual grate, and hence parallel to the other linear-shaped layout features in the given level. Therefore, it should be understood that the various linear-shaped layout features defined in a layout of a given level are oriented to extend across the given level in a parallel manner.
Also, in the dynamic array architecture, each linear-shaped layout feature is defined to be devoid of a substantial change in direction along its length. The lack of substantial change in direction of a linear-shaped layout feature is considered relative to the line of the virtual grate along which the linear-shaped layout feature is defined. In one embodiment, a substantial change in direction of a linear-shaped layout feature exists when the width of the linear-shaped layout feature at any point thereon changes by more than 50% of the nominal width of the linear-shaped layout feature along its entire length. In another embodiment, a substantial change in direction of a linear-shaped layout feature exists when the width of the linear-shaped layout feature changes from any first location on the linear-shaped layout feature to any second location on the linear-shaped layout feature by more that 50% of the linear-shaped layout feature width at the first location. Therefore, it should be appreciated that the dynamic array architecture specifically avoids the use of non-linear-shaped layout features, wherein a non-linear-shaped layout feature includes one or more bends within a plane of the associated level.
In the dynamic array architecture, variations in a vertical cross-section shape of an as-fabricated linear-shaped layout feature can be tolerated to an extent, so long as the variation in the vertical cross-section shape is predictable from a manufacturing perspective and does not adversely impact the manufacture of the given linear-shaped layout feature or its neighboring layout features. In this regard, the vertical cross-section shape corresponds to a cut of the as-fabricated linear-shaped layout feature in a plane perpendicular to the centerline of the linear-shaped layout feature. It should be appreciated that variation in the vertical cross-section of an as-fabricated linear-shaped layout feature along its length can correspond to a variation in width along its length. Therefore, the dynamic array architecture also accommodates variation in the width of an as-fabricated linear-shaped layout feature along its length, so long as the width variation is predictable from a manufacturing perspective and does not adversely impact the manufacture of the linear-shaped layout feature or its neighboring layout features.
Additionally, different linear-shaped layout features within a given level can be designed to have the same width or different widths. Also, the widths of a number of linear-shaped layout features defined along adjacent lines of a given virtual grate can be designed such that the number of linear-shaped layout features contact each other so as to form a single linear-shaped layout feature having a width equal to the sum of the widths of the number of linear-shaped layout features.
Within a given level defined according to the dynamic array architecture, proximate ends of adjacent, co-aligned linear-shaped layout features may be separated from each other by a substantially uniform gap. More specifically, adjacent ends of linear-shaped layout features defined along a common line of a virtual grate are separated by an end gap, and such end gaps within the level associated with the virtual grate may be defined to span a substantially uniform distance. Additionally, in one embodiment, a size of the end gaps is minimized within a manufacturing process capability so as to optimize filling of a given level with linear-shaped layout features.
Also, in the dynamic array architecture, a level can be defined to have any number of virtual grate lines occupied by any number of linear-shaped layout features. In one example, a given level can be defined such that all lines of its virtual grate are occupied by at least one linear-shaped layout feature. In another example, a given level can be defined such that some lines of its virtual grate are occupied by at least one linear-shaped layout feature, and other lines of its virtual grate are vacant, i.e., not occupied by any linear-shaped layout features. Furthermore, in a given level, any number of successively adjacent virtual grate lines can be left vacant. Also, the occupancy versus vacancy of virtual grate lines by linear-shaped layout features in a given level may be defined according to a pattern or repeating pattern across the given level.
Additionally, within the dynamic array architecture, vias and contacts are defined to interconnect a number of the linear-shaped layout features in various levels so as to form a number of functional electronic devices, e.g., transistors, and electronic circuits. Layout features for the vias and contacts can be aligned to virtual grid, wherein a specification of this virtual grid is a function of the specifications of the virtual grates associated with the various levels to which the vias and contacts will connect. Thus, a number of the linear-shaped layout features in various levels form functional components of an electronic circuit. Additionally, some of the linear-shaped layout features within various levels may be non-functional with respect to an electronic circuit, but are manufactured nonetheless so as to reinforce manufacturing of neighboring linear-shaped layout features. It should be understood that the dynamic array architecture is defined to enable accurate prediction of semiconductor device manufacturability with a high probability.
In view of the foregoing, it should be understood that the dynamic array architecture is defined by placement of linear-shaped layout features on a regular-spaced grate (or regular-spaced grid) in a number of levels of a cell, such that the linear-shaped layout features in a given level of the cell are oriented to be substantially parallel with each other in their traversal direction across the cell. Also, in the dynamic array architecture, prior to PCT processing, each linear-shaped layout feature is defined to be devoid of a substantial change in direction relative to its traversal direction across the cell.
Cell
A cell, as referenced herein, represents an abstraction of a logic function, and encapsulates lower-level integrated circuit layouts for implementing the logic function. It should be understood that a given logic function can be represented by multiple cell variations, wherein the cell variations may be differentiated by feature size, performance, and process compensation technique (PCT) processing. For example, multiple cell variations for a given logic function may be differentiated by power consumption, signal timing, current leakage, chip area, OPC, RET, etc. Additionally, multiple cell variations may be differentiated by sub-layout sequence combination. It should also be understood that each cell description includes the layouts for the cell in each level of a chip, as required to implement the logic function of the cell. More specifically, a cell description includes layouts for the cell in each level of the chip extending from the substrate level up through a particular interconnect level.
Exemplary Embodiments
An exemplary gate electrode configuration is shown in
Also shown in
A sub-resolution shape is defined as a mask feature in a given chip level that will not lithographically resolve during manufacturing. One method to form a sub-resolution shape is to restrict a width of the sub-resolution shape along one dimension to a value that is sufficiently small to ensure that the shape will not lithographically resolve. For example, in one embodiment, a sub-resolution shape is defined in a linear manner such that its cross-section when viewed from the top is substantially rectangular so as to have a length and a width, wherein the width is sufficiently small to ensure that the sub-resolution shape does not resolve. Note that in the following text a “regular layout shape” refers to a layout shape that is not a sub-resolution shape. It should also be understood that the terms “shape” and “feature” are synonymous and can be used interchangeably.
A virtual grate (VG) is defined by a set of virtual lines extending in a parallel manner across a portion of a chip level, wherein adjacent ones of the virtual lines are spaced at a substantially constant pitch. One method for determining a VG includes an operation for identifying design rules that pertain to placement of regular layout shapes, i.e., layout polygons, for a chip level, or portion thereof. The method includes another operation for examining applicable design rules to define the VG such that regular layout shapes can be placed according to the VG and can be placed in optimal proximity to each other, with consideration for placement of regular layout shapes (on multiple levels) that require interconnection to perform a desired function. In one embodiment, a VG is defined globally and is applied to a chip area of arbitrary size, shape, and position. Additionally, regular layout shapes within a given chip area may also be placed according to a combination of virtual grates (VGs).
If operation 601 determines that the space adjacent to the regular layout shape to be reinforced is not large enough to support a sub-resolution feature, the method continues to an operation 604, where an evaluation is made as to whether regular layout shapes in the vicinity may be reconfigured to enable the insertion of a sub-resolution shape. Such reconfiguration may include, but is not limited to, techniques of: changing placement of the regular layout shape under consideration for reinforcement, changing placement of neighboring regular layout shapes and/or neighboring sub-resolution shapes, modification of a given regular layout shape's width dimension to change an edge location of the given regular layout shape to a more favorable one, and/or other layout modification. If the evaluation of reconfigurability in operation 604 is negative, i.e., reconfiguration is not possible, the method terminates. If the evaluation of reconfigurability in operation 604 is positive, i.e., reconfiguration is possible, the method continues to an operation 605.
In operation 605, one or more regular layout shapes and/or sub-resolution shapes in the vicinity of the regular layout shape to be reinforced is reconfigured to enable the insertion of a sub-resolution shape. From the operation 605, the method then proceeds to an operation 602 where a sub-resolution shape is placed so as to reinforce the regular layout shape under consideration. Also, if operation 601 determines that the space adjacent to the regular layout shape to be reinforced is large enough to support insertion of a sub-resolution feature, the method proceeds from operation 601 to operation 602. In one embodiment, the sub-resolution shape is placed in operation 602 so as to be centered upon a virtual line of a VG that is associated with placement of the regular layout shape under consideration.
From operation 602, the method proceeds with an operation 603 for determining whether there is benefit in adding more sub-resolution shapes within the space adjacent to the regular layout shape under consideration. A diminished benefit in adding more sub-resolution shapes may exist when sufficient sub-resolution shapes have already been placed near the regular layout shape under consideration, and when there are no other regular layout shapes in the vicinity that require lithographic reinforcement. If there is insufficient benefit in adding further sub-resolution shapes within the space adjacent to the regular layout shape under consideration, the method terminates. However, if there is a benefit, the method reverts back to operation 601. The method of
In some embodiments, a VG used to place regular layout features in a given chip level may not define allowable placement locations for sub-resolution shapes, or a portion thereof, in the given level. For example, when multiple VGs are used to place regular layout shapes in respective areas of a given chip level, an interface may exist between two or more of the multiple VGs.
Because the multiple VGs of the given level can be defined independently from each other, it is possible that the VGs will not co-align at the VG interface. Therefore, it is necessary to evaluate a solution for placing one or more regular layout shapes and/or one or more sub-resolution shapes at the VG interface. In this regard, at least two situations may occur. A first situation (Situation 1) is defined by placement of a regular layout feature over the VG interface. A second situation (Situation 2) is defined by placement of one or more sub-resolution shapes at or near the VG interface, without placement of a regular layout shape over the VG interface.
In the region between the neighboring outermost regular layout features 332 and 336 that extends across the VG interface 360, a local sub-resolution virtual grate (LSVG) is defined by virtual lines 370-377. More specifically, the LSVG is defined by a number of parallel virtual lines 370-377 spaced at a constant pitch. It should be understood that the LSVG is defined independently from both the first VG (301-314) of the first chip area and the second VG (315-327) of the second chip area. Also, the LSVG is defined such that the set of virtual lines 370-377 that define the LSVG is centered within the space between the neighboring outermost regular layout features 332 and 336 of the two interfacing VG areas. For example, The sub-resolution features 380-387 are placed according to the LSVG 370-377.
From the operation 1001, the method proceeds with a decision operation 1003 for determining whether or not there is a regular layout shape placed parallel to the first selected edge 1101A and facing the first selected edge 1101A. If there is not a regular layout shape facing the first selected edge 1101A, the method continues with an operation 1019 of
From the operation 1105, the method proceeds with an operation 1007 for determining a window of lithographic reinforcement for each of the first and second selected edges, 1101A and 1103A respectively, that is to be lithographically reinforced. The window of lithographic reinforcement, also referred to as reinforcement window, for a given regular layout shape edge represents an allowable layout area within which a sub-resolution shape can be placed to provide lithographic reinforcement to the given regular layout shape edge, without causing adverse lithographic effects on the regular layout shape to be reinforced or on other neighboring layout shapes whether they be regular layout shapes or sub-resolution shapes. It should be understood that in one embodiment determination of the reinforcement window for a given regular layout shape edge is predicated on the sub-resolution shape being placed parallel to the given regular layout shape edge.
In one embodiment, the operation 1007 includes an operation for determining a minimum space permitted between each of the first and second selected edges, respectively, and a sub-resolution shape such that undesired lithographic effects are prevented. Examples of undesired lithographic effects in this respect may include, but are not limited to, unintentional resolution of a sub-resolution shape, unintentional distortion of a layout shape that should be resolved (regular layout shape), or other adverse effects. For example, with regard to
Also, in the above-mentioned embodiment, the operation 1007 includes an operation for determining a maximum space permitted between each of the first and second selected edges, respectively, and a sub-resolution shape such that undesired effects are prevented. An example of an undesired effect in this respect may be that the regular layout shape to be lithographically reinforced does not receive lithographic reinforcement due to the sub-resolution shape being placed too far away therefrom. For example, with regard to
From the operation 1007, the method proceeds with a decision operation 1009 for determining whether or not a space between the first and second selected edges supports insertion of a sub-resolution shape, wherein this determination is based on the reinforcement windows determined in operation 1007 for each of the first and second selected edges, respectively. For example, with regard to
In one embodiment, if there is overlap of the reinforcement windows associated with the first and second selected edges, or if there is a space between the reinforcement windows associated with the first and second selected edges, then the space between the first and second selected edges will support insertion of a sub-resolution shape. Otherwise, the space between the first and second selected edges may not support insertion of a sub-resolution shape. For example, with regard to
If operation 1009 determines that the space between the first and second selected edges cannot support insertion of a sub-resolution shape, the method proceeds with an operation 1011 for determining whether or not the regular layout shapes that include the first and second selected edges can be reconfigured, e.g., have their placements in the layout adjusted, to support insertion of a sub-resolution shape therebetween. If the regular layout shapes that include the first and second selected edges cannot be reconfigured, then the method concludes without insertion of a sub-resolution shape between the first and second selected edges. However, if the regular layout shapes that include the first and second selected edges can be reconfigured, then an operation 1013 is performed to reconfigure one or both of these regular layout shapes such that at least one sub-resolution shape can be placed therebetween. It should be understood that the operation 1013 may include reconfiguration of regular layout shapes beyond the regular layout shapes that include the first and second selected edges.
From the operation 1013, the method proceeds with an operation 1015. Also, with reference back to operation 1009, if it is determined that the space between the first and second selected edges can support insertion of a sub-resolution shape, the method proceeds from operation 1009 to the operation 1015. In the operation 1015, placement locations for one or more sub-resolution shapes between the first and second selected edges are determined. The placement locations are determined such that the one or more sub-resolution shapes are placed within the allowable reinforcement windows associated with each of the first and second selected edges, and such that no sub-resolution shape violates the allowable reinforcement windows associated with each of the first and second selected edges. For example, with regard to
With reference back to operation 1003 of
From the operation 1021, the method proceeds with an operation 1023 in which a determination is made as to whether or not further lithographic reinforcement of the regular layout shape that includes the selected edge is appropriate. If it is determined that placement of an additional sub-resolution shape is not appropriate, then the method concludes. Otherwise, if it is determined that placement of an additional sub-resolution shapes is appropriate, the method reverts back to the operation 1021. It should be understood that the appropriateness of further lithographic reinforcement by way of an additional sub-resolution shape insertion is based on consideration of whether the additional sub-resolution shape will provide meaningful reinforcement to the regular layout shape, and whether the additional sub-resolution shape will adversely compromise the non-resolution of previously placed sub-resolution shapes, and whether sufficient layout area is available for placement of an additional sub-resolution shape.
The method of
If decision operation 1051 determines that two sub-resolution shapes can be inserted between the currently selected edges, then the method proceeds with an operation 1057 for inserting two sub-resolution shapes parallel to the currently selected edges, between the currently selected edges, and respectively within the reinforcement windows associated with each of the currently selected edges. It should be appreciated that in one embodiment each of the two sub-resolution shapes is inserted at a layout position to maximize their reinforcement impact on a regular layout shape, without causing resolution of any previously inserted sub-resolution shape. In one embodiment, each of the two sub-resolution shapes is inserted at the minimum spacing of the reinforcement window associated with each of the currently selected edges, respectively. For example, in
Additionally, it should be understood that in an embodiment where the two regular layout shapes are spaced sufficiently apart, the two sub-resolution shapes can be inserted between the currently selected edges so as to comply with the minimum spacing requirement between reinforcement windows and their respective regular layout shapes, and so as to comply with the minimum spacing requirement between adjacent sub-resolution shapes, and yet be inserted beyond either of the reinforcement windows associated with the regular layout shapes to be reinforced. It should be understood that in this embodiment, the sub-resolution shapes inserted beyond either of the reinforcement windows associated with the regular layout shapes may serve to amplify the lithographic reinforcement of the regular layout shapes as provided by sub-resolution shapes that are inserted within the neighboring reinforcement windows.
From the operation 1057, the method proceeds with an operation 1059 in which facing edges of the two previously inserted sub-resolution shapes are designated as the currently selected edges. For example, with regard to
If decision operation 1051 determines that two sub-resolution shapes cannot be inserted between the currently selected edges, then the method proceeds with a decision operation 1053 for determining whether regular layout shapes and/or previously inserted sub-resolution shapes can be reconfigured to support insertion of two sub-resolution shapes within the layout space between the currently selected edges. It should be understood that reconfiguration of regular layout shapes should be done so as to ensure that the reconfigured regular layout shapes remain compliant with applicable design rules and/or applicable architecture specifications, e.g., dynamic array architecture specifications. It should also be understood that reconfiguration of previously inserted sub-resolution shapes should be done so as to ensure that the reconfigured sub-resolution shapes remain within their associated reinforcement windows and do not cause resolution of sub-resolution shapes during manufacturing. Also, it should be noted that as regular layout shapes are reconfigured, the configuration of their corresponding reinforcement windows will follow suit, and some of the reinforcement windows may change in size and/or proximity to their respective regular layout shape.
If decision operation 1053 determines that regular layout shapes and/or previously inserted sub-resolution shapes can be reconfigured to support insertion of two sub-resolution shapes within the layout space between the currently selected edges, then the method proceeds with an operation 1055 for reconfiguring one or more regular layout shapes and/or one or more sub-resolution shapes to support insertion of two sub-resolution shapes between the currently selected edges. Such reconfiguration may include, but is not limited to, the techniques of: 1) changing placement location of one or more regular layout shapes to be lithographically reinforced, 2) changing placement location of one or more neighboring layout shapes (including regular layout shapes and/or sub-resolution shapes), 3) modification of a given regular layout shape dimension to change its edge location. From the operation 1055, the method proceeds to the operation 1057 for inserting two sub-resolution shapes, as previously discussed.
If decision operation 1053 determines that regular layout shapes and/or previously inserted sub-resolution shapes cannot be reconfigured to support insertion of two sub-resolution shapes within the layout space between the currently selected edges, then the method proceeds with an operation 1061 for determining whether the layout space between the currently selected edges supports insertion of one sub-resolution shape. In one embodiment, the currently selected edges at operation 1061 correspond to facing edges of two parallel regular layout shapes. In this embodiment, if the distance extending perpendicularly between the currently selected edges is greater than or equal to the sum of the minimum spaces between the regular layout shapes and their corresponding reinforcement windows, then the layout space between the currently selected edges supports insertion of one sub-resolution shape. For example, with reference back to
In another embodiment, the currently selected edges at operation 1061 correspond to facing edges of two previously inserted sub-resolution shapes. In this embodiment, if the distance extending perpendicularly between the currently selected edges is at least twice the minimum required separation distance between adjacent sub-resolution shapes (so as to ensure that sub-resolution shapes do not resolve during manufacturing), then the layout space between the currently selected edges supports insertion of one sub-resolution shape.
If decision operation 1061 determines that one sub-resolution shapes can be inserted between the currently selected edges, then the method proceeds with an operation 1067 for inserting one sub-resolution shape parallel to the currently selected edges and between the currently selected edges. In one embodiment, the one sub-resolution shape is placed so as to bisect the layout space between the currently selected edges. In another embodiment, the one sub-resolution shape is placed closer to one of the currently selected edges than the other, so as to preferentially reinforce resolution of one regular layout shape relative to the other. It should be appreciated, though, that placement of the one sub-resolution in this embodiment satisfies the minimum spacing required between adjacent sub-resolution shapes.
Additionally, it should be understood that the one sub-resolution shape in operation 1067 may or may not fall within a reinforcement window. For example, in an embodiment where the two regular layout shapes are spaced sufficiently apart, the one sub-resolution shape can be inserted between the currently selected edges so as to comply with the minimum spacing requirement between reinforcement windows and their respective regular layout shapes, and so as to comply with the minimum spacing requirement between adjacent sub-resolution shapes, and yet be inserted beyond either of the reinforcement windows associated with the regular layout shapes to be reinforced. It should be understood that in this embodiment, the one sub-resolution shape inserted beyond either of the reinforcement windows associated with the regular layout shapes may serve to amplify the lithographic reinforcement of the regular layout shapes as provided by sub-resolution shapes that are inserted within the neighboring reinforcement windows.
With reference back to the decision operation 1061, if the minimum space between one of the regular layout shapes and its reinforcement window encroaches within the minimum space between the other regular layout shape and its reinforcement window, then the layout space between the currently selected edges does not support insertion of one sub-resolution shape. For example,
If decision operation 1061 determines that one sub-resolution shapes cannot be inserted between the currently selected edges, then the method proceeds with an operation 1063 for determining whether regular layout shapes and/or previously inserted sub-resolution shapes can be reconfigured to support insertion of one sub-resolution shape within the layout space between the currently selected edges. It should be understood that reconfiguration of regular layout shapes should be done so as to ensure that the reconfigured regular layout shapes remain compliant with applicable design rules and/or applicable architecture specifications, e.g., dynamic array architecture specifications. It should also be understood that reconfiguration of previously inserted sub-resolution shapes should be done so as to ensure that the reconfigured sub-resolution shapes remain within their associated reinforcement windows and do not cause resolution of sub-resolution shapes during manufacturing. Also, it should be noted that as regular layout shapes are reconfigured, the configuration of their corresponding reinforcement windows will follow suit, and some of the reinforcement windows may change in size and/or proximity to their respective regular layout shape.
If decision operation 1063 determines that regular layout shapes and/or previously inserted sub-resolution shapes can be reconfigured to support insertion of one sub-resolution shape within the layout space between the currently selected edges, then the method proceeds with an operation 1065 for reconfiguring one or more regular layout shapes and/or one or more sub-resolution shapes to support insertion of one sub-resolution shape between the currently selected edges. Such reconfiguration may include, but is not limited to, the techniques of: 1) changing placement location of one or more regular layout shapes to be lithographically reinforced, 2) changing placement location of one or more neighboring layout shapes (including regular layout shapes and/or sub-resolution shapes), 3) modification of a given regular layout shape dimension to change its edge location. From the operation 1065, the method proceeds to the operation 1067 for inserting one sub-resolution shape, as previously discussed. If decision operation 1063 determines that regular layout shapes and/or previously inserted sub-resolution shapes cannot be reconfigured to support insertion of one sub-resolution shape within the layout space between the currently selected edges, then the method concludes. Also, following the operation 1067, the method concludes.
In another embodiment, a sub-resolution shape is inserted to replace a regular layout shape that has been removed from the layout for any number of reasons, such as to reduce capacitance.
In some embodiments it may be possible for sub-resolution shapes to inadvertently resolve into a manufactured shape. Causes for undesired resolution of a given sub-resolution shape may include a length of the given sub-resolution shape, unintentional lithographic reinforcement of the given sub-resolution shape by other layout shapes, or other causes. In one embodiment, to prevent resolution of sub-resolution shapes, the sub-resolution shapes are segmented along their length. For example,
Additionally, when segmented sub-resolution shapes are placed next to each other, the gaps between segments of one segmented sub-resolution shape can be positioned in a particular manner with respect to the gaps between segments of an adjacent segmented sub-resolution shape. For example, in one embodiment, the segment-to-segment gaps of one segmented sub-resolution shape may be offset from the segment-to-segment gaps of an adjacent segmented sub-resolution shape, such that the segment-to-segment gaps of the two segmented sub-resolution shapes do not align in a direction perpendicular to the two segmented sub-resolution shapes. In another embodiment, the segment-to-segment gaps of two adjacent segmented sub-resolution shapes may be aligned in a direction perpendicular to the two segmented sub-resolution shapes.
For example,
It should be understood that the method for sub-resolution shape utilization as disclosed herein can be implemented in a layout that is stored in a tangible form, such as in a digital format on a computer readable medium. For example, the layout including the sub-resolution shapes placed according to the methods as disclosed herein can be stored in a layout data file of one or more cells, selectable from one or more libraries of cells. The layout data file can be formatted as a GDS II (Graphic Data System) database file, an OASIS (Open Artwork System Interchange Standard) database file, or any other type of data file format suitable for storing and communicating semiconductor device layouts. Also, multi-level layouts utilizing the sub-resolution shapes placed according to the methods as disclosed herein can be included within a multi-level layout of a larger semiconductor device. The multi-level layout of the larger semiconductor device can also be stored in the form of a layout data file, such as those identified above.
Also, the invention described herein can be embodied as computer readable code on a computer readable medium. For example, the computer readable code can include the layout data file within which one or more layouts including the sub-resolution shapes placed according to the methods as disclosed herein are stored. The computer readable code can also include program instructions for selecting one or more layout libraries and/or cells that include a layout having sub-resolution shapes defined therein, wherein the sub-resolution shapes are placed according to the methods as disclosed herein. The layout libraries and/or cells can also be stored in a digital format on a computer readable medium.
The computer readable medium mentioned herein is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data may be processed by other computers on the network, e.g., a cloud of computing resources.
The embodiments of the present invention can also be defined as a machine that transforms data from one state to another state. The data may represent an article, that can be represented as an electronic signal and electronically manipulate data. The transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data. The transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object. In some embodiments, the manipulation can be performed by a processor. In such an example, the processor thus transforms the data from one thing to another. Still further, the methods can be processed by one or more machines or processors that can be connected over a network. Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine.
It should be further understood that the layouts as disclosed herein can be manufactured as part of a semiconductor device or chip. In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on a semiconductor wafer. The wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.
This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/059,712, filed Jun. 6, 2008, entitled “Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology.” This application is a continuation-in-part application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/013,342, filed Jan. 11, 2008 now U.S. Pat. No. 7,917,879, entitled “Semiconductor Device with Dynamic Array Section,” which claims priority under 35 U.S.C. 119(e) to both U.S. Provisional Patent Application No. 60/963,364, filed Aug. 2, 2007, and to prior U.S. Provisional Patent Application No. 60/972,394, filed Sep. 14, 2007. This application is also a continuation-in-part application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/212,562, filed Sep. 17, 2008 now U.S. Pat. No. 7,842,975, entitled “Dynamic Array Architecture,” which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 11/683,402, filed Mar. 7, 2007 now U.S. Pat. No. 7,446,352, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/781,288, filed Mar. 9, 2006. The disclosure of each above-identified patent application is incorporated herein by reference in its entirety.
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| Number | Date | Country |
|---|---|---|
| 1394858 | Mar 2004 | EP |
| 1670062 | Jun 2006 | EP |
| 2860920 | Apr 2005 | FR |
| 10-116911 | May 1998 | JP |
| 2002-258463 | Sep 2002 | JP |
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| WO 2007103587 | Sep 2007 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20090300574 A1 | Dec 2009 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61059712 | Jun 2008 | US | |
| 60963364 | Aug 2007 | US | |
| 60972394 | Sep 2007 | US | |
| 60781288 | Mar 2006 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11683402 | Mar 2007 | US |
| Child | 12212562 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12013342 | Jan 2008 | US |
| Child | 12479674 | US | |
| Parent | 12212562 | Sep 2008 | US |
| Child | 12013342 | US |
