Patent Application
20100267237
The present invention generally relates to methods for fabricating semiconductor devices, and more particularly relates to methods for fabricating FinFET semiconductor devices using ashable sacrificial mandrels.
Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building blocks of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices having a planar architecture and a single gate electrode, decreasing transistors size has traditionally been the primary means of fabricating ever increasing numbers of transistors on a single device chip.
Transistors having a non-planar architecture and more than one gate electrode have also been investigated as a means of increasing device density. A FinFET is a type of non-planar transistor that has one or more conductive fins that are raised above the substrate surface and extend between a source and drain region providing a channel for the device. Common methods of forming finned structures include the formation a sacrificial mandrel overlying a silicon substrate followed by the formation of thin spacers on the sidewalls of the mandrel. The mandrel then is subsequently selectively removed leaving the sidewall spacers standing intact on the surface of the substrate. Because of the support provided by the mandrel, spacers can be formed with a smaller base critical dimension (CD) and a larger aspect ratio (the ratio of the height of a feature to its smallest base CD) than would be possible using conventional lithographic means.
Typically, mandrels may be fabricated from an inorganic and/or dielectric material such as polycrystalline silicon or silicon oxide (SiOx) where x is a number greater than zero, silicon nitride (Si3N4), silicon oxynitride (SiON), or the like. Spacers generally comprise a dielectric material different in composition than that of the mandrel and chosen to facilitate high mandrel-to-spacer etch selectivity. Such highly selective etch processes help to maximize CD control of spacers and to minimize device defect levels by minimizing erosion of the sidewall spacers during the mandrel etch. Certain wet etchants such as, for example, hydrochloric acid (HCl) solutions offer improved etch selectivity compared with dry etch processes in the removal of mandrel materials such as polycrystalline silicon. However, wet etchants can exacerbate spacer collapse and increase defect count because of the viscous and capillary forces they generate.
Accordingly, it is desirable to provide methods for fabricating FinFET transistor devices using ashable sacrificial mandrels. Further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel.
A method is provided for fabricating a semiconductor device on and in a semiconductor substrate in accordance with another exemplary embodiment of the invention. The method comprises the steps of forming an ashable material layer overlying the substrate and patterning the ashable material layer to form an ashable mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the ashable mandrel, and the ashable mandrel is removed using an ashing process having an etch rate of the ashable mandrel relative to the sidewall spacers of at least about 50:1. The substrate is etched using the sidewall spacers as an etch mask after removal of the ashable mandrel.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
The various embodiments of the present invention describe methods for fabricating FinFET transistors using ashable sacrificial mandrels. Ashable materials such as, for example, amorphous carbon are substituted for conventional inorganic sacrificial mandrel materials such as SiOx, Si3N4, polycrystalline silicon, SiON, and the like, and are removed following spacer formation using a highly selective oxygen-based (O2) plasma ashing process. In accordance with one embodiment, the ashing process removes the ashable sacrificial mandrel with at least a 50:1 etch selectivity, or with an etch rate that is at least 50 times faster than the etch rate for dielectric/inorganic spacer materials. Materials suitable as ashable sacrificial mandrels also have physical properties that are sufficient to withstand exposure to etch processes needed for mandrel formation, and the subsequent thermal processing budget (time and temperature) associated with deposition and etch processes needed for the formation of sidewall spacers.
Referring to
An ashable material layer 116 is formed overlying thin silicon layer 106. Ashable material layer 116 may comprise any suitable material that is removable using a dry, plasma, O2-based ashing process. As will be described in further detail below, layer 116 will be patterned to form mandrels and therefore should have suitable thermal properties to withstand such patterning. Sidewall spacers will also be formed on the mandrels and therefore a material suited for use as layer 116 can also withstand the additional subsequent deposition and etch processes used to form these spacers. In one embodiment, ashable material layer 116 comprises amorphous carbon (a-C). As used herein, the term amorphous carbon also includes hydrogenated amorphous carbon (a-C:H) and further includes any microstructure such as, for example, diamond-like amorphous carbon (DLC), polymer-like amorphous carbon (PLC), or any combination of these microstructures. Further, the term amorphous carbon may be used without limitation as to the percentage of the material having a particular polycrystalline microstructure. The DLC microstructure provides a film with a higher density and hardness and a lower hydrogen (H) content than a PLC microstructure. Amorphous carbon may be deposited using a suitable chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) process based on a hydrocarbon gas or mixture of hydrocarbon gases such as, for example, acetylene (C2H2), propylene (C3H6), or the like, and may also include hydrogen (H2). Deposition of a-C films may be performed using, for example, the ashable hard mask (AHM) process (available from Novellus Systems, Inc., San Jose, Calif.) run on the Vector® Express PECVD platform, or the Producer PECVD platform (available from Applied Materials, Inc., Santa Clara, Calif.).
In another embodiment, ashable material layer 116 may be a suitable thermoplastic polymeric material such as, for example, a thermoplastic polyimide, or a thermosetting polymeric material such as, for example, a thermosetting polyimide, an epoxy, or the like having adequate thermal properties as described above. Such a polymeric material may be applied in any manner, and preferably in a dissolved state using, for example, a suitable spin-on coating and post-application bake sequence. Because sidewall spacers will be subsequently formed adjacent the sidewalls of sacrificial mandrels made from ashable material layer 116, the thickness of layer 116 will be selected based, at least in part, upon the desired height of these spacers. The spacer height, in turn, will depend upon the etch selectivity of the subsequent pattern transfer of the spacers into the substrate to form fin structures in conjunction with the desired fin height. Ashable material layer 116 may therefore have any thickness consistent with these considerations in conjunction with the overall design of device 100. In one embodiment, ashable material layer 116 has a thickness of from about 100 nanometers (nm) to about 1 micron (μm). A suitable patterned soft mask 124 then is formed overlying ashable material layer 116 using conventional photoresist and lithography processes.
Ashable material layer 116 is anisotropically etched using soft mask 124 as an etch mask to form sacrificial mandrels 132, as illustrated in
Next, a sidewall spacer layer 128 comprising an inorganic dielectric material such as, for example, silicon nitride, silicon oxynitride, or preferably silicon oxide is conformally blanket-deposited overlying the surface of device 100 including sacrificial mandrels 132. Sidewall spacer layer 128 may be deposited, for example, by a PECVD process using silane (SiH4) and either nitrous oxide (N2O) or O2 to form a silicon oxide layer, or by using SiH4 and NH3 or N2 in the presence of an argon (Ar) plasma to form a silicon nitride layer. Layer 128 may also be deposited using low pressure chemical vapor deposition (LPCVD) using tetraethyl orthosilicate (TEOS: Si(OC2H5)4), or dichlorosilane (SiH2Cl2) and N2O to form a silicon oxide layer. In one embodiment, sidewall spacer layer 128 has a thickness of from about 100 nm to about 1 μm. As described in greater detail below, sidewall spacer layer 128 will form sidewall spacers that will be used as an etch mask for etching thin silicon layer 106 to form fin structures. The width, or smallest base CD of these spacers is a significant factor in defining the width of the final fin structures, and is determined, at least in part, by the thickness of layer 128.
The method continues with the anisotropic etch of sidewall spacer layer 128 to form sidewall spacers 136 on the sidewalls of sacrificial mandrels 132, as illustrated in
Accordingly, methods have been provided for the fabrication of FinFET transistor devices using ashable sacrificial mandrels. Such mandrels are formed by the deposition and patterning of a layer of an ashable material such as amorphous carbon overlying a semiconductor substrate. Sidewall spacers comprising, for example, a dielectric material are formed on the sidewalls of the sacrificial mandrels followed by the removal of the mandrels using a dry, plasma, O2-based ashing process. The ashing process removes the ashable sacrificial mandrel material with a high level of selectivity relative to surrounding spacer and substrate materials. Because of the high etch selectivity, spacer materials may be chosen based upon their etch selectivity as hard etch masks to the substrate material, rather than based upon selectivity to both substrate and mandrel materials. In addition, removal of the mandrel in a highly selective manner reduces spacer erosion during this process enabling improved CD control of these features. Further, defects that might otherwise be caused by viscous and capillary forces associated with wet etchants are avoided by using a dry ashing process. Accordingly, fabrication of FinFET transistors having fin structures with improved CD control and fewer defects is enabled via a processing sequence that may be easily incorporated into a typical semiconductor fabrication line.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
