The present disclosure relates to methods for forming integrated circuit structures having recessed gate spacers and related integrated circuit structures.
A typical integrated circuit (IC) chip includes a stack of several levels, or sequentially formed layers, of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) or connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as complementary metal-oxide semiconductor (CMOS), layers are formed on a wafer to form the devices on a surface of the wafer. The surface may be the surface of a semiconductor layer on a semiconductor on insulator (SOI) wafer. A simple FinFET includes a gate layer on a semiconductor surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin “fin” extending from the substrate, for example, etched into a silicon layer of the substrate. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate structure, a conductive channel region forms between the drain region and the source region. A double gate may be beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
As FinFETs continue to shrink in size (e.g., 7 nm and beyond), a shorting between source/drain contacts and gate structures or gate contacts becomes more of a problem due to the relatively small aspect ratio of the opening in which source/drain contacts may be formed. As known in the art, the aspect ratio is representative of the height of a structure divided by its width. In addition, the process window for forming source/drain contacts is quite small and therefore, it may be difficult to form such contacts.
A first aspect of the disclosure is directed to method for forming an integrated circuit structure. The method may include: forming a first dummy gate over a fin and forming a second dummy gate over the fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer of the first dummy gate and a second gate spacer of the second dummy gate, the opening exposing a source/drain region within the fin; recessing the first gate spacer and the second gate spacer to a height below a height of the first dummy gate and the second dummy gate; forming an etch stop layer within the opening over the exposed source/drain region such that the etch stop layer extends vertically along the recessed first gate spacer and the recessed second gate spacer; forming a dielectric fill over the etch stop layer within the opening and on the etch stop layer to substantially fill the opening; replacing the first dummy gate with a first replacement metal gate (RMG) structure and replacing the second dummy gate with a second RMG structure; recessing the first RMG structure and the second RMG structure; and forming a gate cap layer over each of the first RMG structure and the second RMG structure.
A second aspect of the disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a fin including a source/drain region therein; a first replacement metal gate (RMG) structure and a second RMG structure over the fin on opposing sides of the source/drain region, each RMG structure having a pair of gate spacers disposed on opposing sidewalls thereof; a first gate spacer of the pair of gate spacers of the first RMG structure having a height that is greater than a height of the first RMG structure; a second gate spacer of the pair of gate spacers of the second RMG structure having a height that is greater than a height of the second RMG structure; and an etch stop layer over the source/drain region within the fin and extending vertically along sidewalls of and over a top surface of each of the first gate spacer and the second gate spacer.
A third aspect of the disclosure is directed to method for forming an integrated circuit structure. The method may include: forming a first dummy gate over a fin and forming a second dummy gate over the fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer of the first dummy gate and a second gate spacer of the second dummy gate, the opening exposing a source/drain region within the fin; recessing the first gate spacer and the second gate spacer to a height below a height of the first dummy gate and the second dummy gate; forming an etch stop layer within the opening over the exposed source/drain region such that the etch stop layer extends vertically along the recessed first gate spacer and the recessed second gate spacer; forming a dielectric fill over the etch stop layer within the opening to substantially fill the opening; replacing the first dummy gate with a first replacement metal gate (RMG) structure and replacing the second dummy gate with a second RMG structure; recessing the first RMG structure and the second RMG structure, wherein the recessing of the first RMG structure and the second RMG structure includes recessing the first RMG structure and the second RMG structure to a height below the height of the first gate spacer and the second gate spacer; forming a gate cap layer over each of the first RMG structure and the second RMG structure; removing the dielectric fill to expose the etch stop layer thereunder; and forming a source/drain contact over the etch stop layer.
The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.
The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
The present disclosure relates to methods for forming integrated circuit structures having recessed gate spacers and related integrated circuit structures. The present disclosure provides for methods and structures having recessed gate spacers and replacement metal gate structures such that a height of the recessed gate spacers are greater than a height of the replacement metal gate structures. More specifically, the methods described herein include recessing gate spacers disposed between adjacent dummy gates to increase a width of an opening disposed over a source/drain region between the adjacent dummy gates. By increasing a width of the opening, the aspect ratio (aspect ratio=height of the opening/width of the opening) of the opening is increased. In this way, the process window for forming a source/drain contact therein is improved. In addition, after the width of the opening is increased, the dummy gates are replaced with replacement metal gate (RMG) structures, and the RMG structures are recessed to a height below a height of the recessed gate spacers. As a result, less shorting occurs between the RMG structures and later formed source/drain contacts.
IC structure 100 may also include a set of fins 104 and an isolation region 106, e.g., shallow trench isolation (STI), disposed between adjacent fins and over substrate 102. Isolation region 106 may include any suitable isolation material, e.g., silicon oxide. Isolation region 106 may be formed by any suitable process including etching a trench (not shown) within substrate 102, and filling, e.g., by depositing, the trench with the isolation material. Set of fins 104 may be formed from substrate 102 by any suitable process including one or more photolithography and etch processes. While four fins are shown, it is to be understood that any number of fins may be employed without departing from aspects of the disclosure.
As used herein, the term “depositing” may include any now known or later developed technique appropriate for deposition, including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.
As used herein, “etching” generally refers to the removal of material from a substrate or structures formed on the substrate by wet or dry chemical means. In some instances, it may be desirable to selectively remove material from certain areas of the substrate. In such an instance, a mask may be used to prevent the removal of material from certain areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etching may be used to selectively dissolve a given material and leave another material relatively intact. Wet etching is typically performed with a solvent, such as an acid. Dry etching may be performed using a plasma which may produce energetic free radicals, or species neutrally charged, that react or impinge at the surface of the wafer. Neutral particles may attack the wafer from all angles, and thus, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases from a single direction, and thus, this process is highly anisotropic. A reactive-ion etch (RIE) operates under conditions intermediate between sputter etching and plasma etching and may be used to produce deep, narrow features, such as trenches.
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The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material may have the same crystalline characteristics as the deposition surface on which it may be formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface may take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes may be selective to forming on semiconductor surfaces, and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.
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At this point, IC structure 100 may include fin 104 having source/drain region 126 therein. First RMG structure 150a and second RMG structure 150b may be disposed over fin 104 on opposing sides of source/drain region 126. Each RMG structure 150 may include a pair of gate spacers 118 disposed on opposing sidewalls thereof. First gate spacer 118a of first RMG structure 150a may have a height that is greater than a height of first RMG structure 150a. Second gate spacer 118b of second RMG structure 150b may have a height that is greater than a height of second RMG 150b. Etch stop layer 136 may be disposed over source/drain region 126 and extend vertically along sidewalls of and over a top surface of each of first gate spacer 118a and second gate spacer 118b. Further, IC structure 100 may include gate cap layer 152 over each of first and second RMG structures 150a, 150b. Etch stop layer 136 may extend vertically along a sidewall of gate cap layer 152 as shown in
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The present disclosure provides for methods and structures having recessed gate spacers and replacement metal gate structures such that a height of the recessed gate spacers are greater than a height of the replacement metal gate structures. More specifically, the methods described herein include recessing gate spacers disposed between adjacent dummy gates to increase a width of an opening disposed over a source/drain region between the adjacent dummy gates. By increasing a width of the opening, the aspect ratio (aspect ratio =height of the opening/width of the opening) of the opening is increased. In this way, the process window for forming a source/drain contact therein is improved. In addition, after the width of the opening is increased, the dummy gates are replaced with replacement metal gate (RMG) structures, and the RMG structures are recessed to a height below a height of the recessed gate spacers. As a result, less shorting occurs between the RMG structures and later formed source/drain contacts.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the terms “first,” “second,” and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s). “Substantially” refers to largely, for the most part, entirely specified or any slight deviation which provides the same technical benefits of the disclosure.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.