Patent Application
20100167552
The present invention relates to fabrication of integrated circuits, and more specifically to methods for particle removal during the fabrication of integrated circuits.
Cleaning or surface preparation of silicon wafers is important in integrated circuit (IC) manufacturing processes. In a typical IC manufacturing process, 20% or more of the fabrication sequence is dedicated to cleaning. The challenges of cleaning technology are multiplied by the varied types of microelectronic layers, topographies, and contaminants to be removed in front-end-of-line (FEOL) and back-end-of-line (BEOL) cleaning processes. That is, as the number and complexity of IC process steps increases, the number of opportunities for generating particles is also significantly increased. Therefore, removal of these particles has become increasingly important, especially as minimum feature dimensions are decreased.
In general, as the minimum feature dimension has been decreased, smaller-dimensioned particles have increasingly become a more significant source of yield-impacting defects in the IC manufacturing process. Unfortunately, such smaller-dimensioned particles are generally difficult to remove since the ratio of the force of adhesion to removal increases for smaller-dimensioned particles. Aggressive particle removal techniques are available that remove such small particles, but are generally not suitable for cleaning some types of microelectronic layers.
This Summary is provided to comply with 37 C.F.R. §1.73, presenting a summary of the invention to briefly indicate the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Embodiments of the invention provide methods for reducing defect density during the IC device manufacturing process using cryogenic cleaning processes, and in particular, particles than can lead to micromask-induced yield-limiting defects. That is, defects resulting from features formed during incomplete or non-uniform removal of masking layers prior to etch processes and that are subsequently dislodged. The micromasks can result from micromask-prone processes, such as planarization processes, lithography processes, etch processes, and post-etch cleaning processes.
In a first embodiment of the present invention, a method of manufacturing an IC device is provided. The method includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece and processing the dielectric layer to form a plurality of apertures in the dielectric layer. The processing includes at least one micromask-prone process. The method also includes cryogenically treating the workpiece subsequent to the processing step. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process. As used herein, “maintains the plurality of apertures” refers to the dimensions of the apertures or openings not being measurably altered by the cryogenic treatment. For example, in the case of a dielectric contact layer process, the dimensions of the contact openings in the dielectric following cryogenic treatment according to an embodiment of the invention appear unchanged as imaged by conventional imaging methods.
In a second embodiment of the present invention, a method of manufacturing an IC is provided. The method includes providing a substrate having a semiconducting surface, forming a plurality of devices on or in the semiconducting surface, and depositing at least one dielectric layer over the semiconducting surface. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer for forming contacts to the plurality of devices, where the processing includes at least one micromask-prone process. The method further includes cryogenically treating the dielectric layer subsequent to the processing step. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process.
In a third embodiment of the present invention, a method of manufacturing an IC is provided. The method includes providing a substrate having a semiconducting surface and depositing at least dielectric masking layer over a portion of the semiconducting surface. The method also includes processing the dielectric masking layer to form a plurality of apertures in the dielectric masking layer and the semiconducting surface. The processing includes at least one micromask-prone process. The method further includes subsequent to the processing step, cryogenically treating the substrate. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the instant invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One having ordinary skill in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts can occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
Embodiments of the invention provide methods for reducing defect density during the IC device manufacturing process and in particular, particles than can lead to micromask-induced yield-limiting defects. The term “micromask”, as used herein, refers to masking material, with respect to an etch process for fabrication of the IC device, randomly formed in a region of a substrate and generally having dimensions on the order of the features of an IC device or smaller. Micromasks can be formed by non-uniform etching or polishing processes, deposition of masking materials, or re-deposition of materials during an IC device fabrication process.
For example, a conventional contact layer process for advanced semiconductor manufacturing process generally includes deposition of a dielectric contact layer (e.g., silicon oxide comprising materials such as undoped silicate glass, phosphosilicate glass, borophosphosilicate glass), a chemical mechanical polishing (CMP) step to provide planarization of the dielectric contact layer, and etching of contact openings in the dielectric contact layer. However, conventional CMP processes typically provide poor uniformity in the dielectric contact layer at the edge of the wafer, resulting in micro-masking around the edge of the wafer and formation of vertically elongated dielectric features at the edge of the wafer during the contact etch process. That is, the formation of features at the surface of the dielectric contact layer having a high aspect ratio. These vertically elongated features are generally fragile and are often dislodged during post-etch wet cleaning processes to form particles. As a result, the dislodged vertically elongated features can be spread out over the surface of the wafer and can block contact openings in the dielectric contact layer, thereby preventing the contact openings from being filled during a contact metal deposition process (e.g., tungsten fill process). If a significant number of such particles are present during the contact metal deposition process, a significant yield loss is possible.
Although embodiments of the present invention will be described in terms of an exemplary contact etch process, the various embodiments of the present invention are not limited in this regard. The various embodiments of the present invention are equally applicable to other processes that are favorable to the formation of micromasks (“micromask-prone processes”) and that can result in the generation of micromask features which can generate yield-impacting particles. For example, similar dielectric features can be formed during back end of the line (BEOL) processing, such as during via formation. In another example, vertically elongated features can be formed during shallow trench isolation (STI) processes. During STI processes, micromasking of the dielectric masking layers, such as silicon oxide (SiOx) and/or silicon nitride (SiNx), can occur. For example, contaminants and defects in the photoresist and other lithography films can also result in randomly formed features. That is, the contaminants and defects can cause inadvertent masking over areas of the wafer surface. Accordingly, during the STI silicon trench process, such micromasked areas may not be properly etched and can result in vertically elongated features. Such features can be dislodged during subsequent processing, resulting in particles that can be transferred to the surface of the wafers and potentially prevent proper STI trench fill.
Although some aggressive cleaning processes are generally available for removing such micromask-induced particles deposited on the wafer surface during etch processes and post-etch wet cleaning processes after micromask-prone processes, such aggressive cleaning processes can introduce additional problems. For example, using aggressive cleaning processes generally results in significant corrosion in front end of the line (FEOL) metal-comprising layers (e.g., metal gates or silicide gate and contacts) formed on the IC. Additionally, such aggressive cleaning processes can cause etching of the dielectrics or other materials, resulting in variation of features, and alteration of the surface of the materials exposed, resulting in variations in contact resistance and/or adhesion of subsequent layers of materials. As a result, the lack of suitable cleaning processes for removing such particles during some types of processes, without measurably impacting device yield or inducing reliability-based failures is needed.
The Present Inventors, however, have discovered that micromask-induced particles, such as the dielectric-comprising (e.g. silicon oxide) vertically elongated features generated during CMP processes of the contact layer process flow, can be significantly reduced by subjecting a workpiece including such particles to a cryogenic cleaning process. As used herein, a “cryogenic cleaning process” refers to a cleaning process in which a fluid is discharged as a cryogenic aerosol comprising gaseous and solid components that is directed toward the surfaces which are to be cleaned or decontaminated. The cryogenic aerosol is generated by discharging a fluid maintained at a high pressure (approximately 50 to 100 psia) into a chamber at a considerably lower pressure (typically 1 psia or less). The resulting expansion of the fluid results in the formation of a cryogenic aerosol including high velocity solid or solid-liquid clusters formed due to evaporative cooling. Therefore, cryogenic cleaning provides a clean based on mechanical action, rather than chemical interactions. The term “microelectronic workpiece”, as used herein, refers to a substrate used for forming an IC device, including but not limited to printed-circuit boards, flat panel displays, hard drives, single and multiple chip modules, and substrates having semiconductor surfaces (e.g. wafers). Cryogenic cleaning processes therefore provide a “dry” cleaning alternative to more conventional wet chemical cleans for particle removal. Furthermore, cryogenic cleaning is able to use non-corrosive, inert substances such as argon, nitrogen, carbon dioxide, or any combination thereof.
The Present Inventors have found that subjecting workpiece surfaces that include particles resulting from the dislodgement of vertically elongated features to such cryogenic cleaning processes does not significantly alter the composition or structure of the exposed workpiece layers. Although various types of inert substances can be used in the various embodiments of the present invention, the Present Inventors have found that a cryogenic clean in accordance with an embodiment of the present invention, such as an argon/nitrogen-based clean, generally maintains features in exposed workpiece surfaces. That is, the dimensions of the features, such as apertures or openings, are not measurably altered by the cryogenic clean. Furthermore, the Present Inventors also have found that a cryogenic clean in accordance with an embodiment of the present invention generally maintains the chemical and physical structure of the exposed workpiece layers in a workpiece. That is, the thicknesses of the exposed layers are not measurably affected by the cryogenic cleaning process. For example, in the case of a contact layer process, the thicknesses of the dielectric contact layer is unchanged as measured by conventional ellipsometric methods. Also, the adhesion properties and the resistance to erosion during subsequent CMP and etch processes (i.e., CMP resistance and etch resistance) are also generally unaffected by the cryogenic cleaning process. For example, in the case of a contact layer process, CMP of the dielectric contact layer and subsequent contact metal planarization processes (e.g., tungsten CMP stopping on the dielectric contact layer) are generally unaffected. Furthermore, contact metals can be deposited on the treated dielectric contact layers and the treated dielectric contact layers can generally be exposed to subsequent CMP processes with little or no alteration of either of these processes. Additionally, the Present Inventors have found that the cryogenic clean generally does not significantly erode the exposed workpiece layers to generate additional particles. Furthermore, the Present Inventors have found that the cryogenic clean also generally results in little or no corrosion of exposed metal-comprising layers in the workpiece.
In the some embodiments of the present invention, the cryogenic clean can be performed using a conventional cryogenic cleaning tool.
The chuck 14 can provide a linear movement within a predetermined range to move the entire side of the workpiece 12 through the jet impingement stream. In some embodiments of the present invention rotational chucks (not shown) can be utilized, whereby rotary movement of the workpiece 12 is produced in order to impinge its surface with the jets from the nozzle 18. The nozzle 18 can also be translatable in the direction parallel to the surface of the wafer (in-plane) in addition to movement of the chuck, or instead of the chuck while the chuck and the wafer remain stationary to accomplish a similar result. The term “chuck”, as used herein, refers to a device which functionally supports an object to be treated. In the case where the chuck 14 moves linearly or rotationally, the chuck 14 also includes the appropriate slide or guide mechanism or turntable. However, where the chuck 14 is stationary, it can be merely a functional support mechanism.
As shown in
To control the fluid dynamics within the treatment chamber 16, a flow separator comprising a baffle plate 34 can be connected to an end of the movable chuck 14 and can extend into the exhaust duct 20. Additionally, a shroud 36 can be provided within the treatment chamber 16 and comprises a plate connected to the treatment chamber 16, such as its upper wall, for controlling flow around the nozzle 18. The purpose of the baffle plate 34 and the shroud 36 is to divide the post-impingement flow into positive streams C and D for preventing recontamination of the surface 13.
As shown in
Also shown in
The nozzle 18 can be adjustable toward or away from the surface 13. The distance x shown in
The following non-limiting Examples serve to illustrate selected embodiments of the invention. It will be appreciated that variations in proportions and alternatives in elements of the components shown will be apparent to those skilled in the art and are within the scope of embodiments of the present invention.
Tests were conducted to demonstrate that a reduced number of defects can be provided by cryogenic cleaning of particles performed in accordance with an embodiment of the present invention. To carry out these tests, a cryogenic cleaning tool commercially available under the registered trademark ANTARES™ from FSI International, Inc., Chaska, Minn., was used. No modifications to the ANTARES™ cryogenic cleaning tool were made. The defect reduction performance of the cryogenic clean was evaluated by comparing particle counts on 300 mm silicon wafers before and after cryogenic cleaning a contact layer process flow, including a micromask-prone process (e.g., CMP process), known to generate a significant amount of particles on the silicon wafer. In particular, the silicon wafers were inspected after a spray tool-based clean following contact opening etch step. At this point in contact layer processing, particles (e.g., dielectric-comprising vertically elongated features) from the edge (i.e., near or at the bevel region) of the silicon wafers are known to be easily knocked into the active device areas of the IC substrates by the spray tool. This can be exacerbated by certain features of the silicon, such as a wafer notch. The defect count results for the spray tool clean process performed is shown in
As shown in
The wafers 308, 310, and 312 were then subjected to a cryogenic cleaning process in accordance with an embodiment of the present invention. In particular, an argon/nitrogen cryogenic cleaning process was used. The process conditions were 246 slpm of argon, 82 slpm of nitrogen, and 400 slpm of a curtain gas. The treatment chamber was held at approximately 50 Torr and a back pressure of 100 psia was provided while the chuck was held at approximately 60° C. A 1 minute, 2-pass process was used. The nozzles were kept stationary at an angle of 45 degrees while the chuck was moved underneath. The result of the cryogenic cleaning is shown in
Furthermore, the dimensions of the features in the contact layer were measured using conventional scanning electron microscope measurements to determine if the dimensions of the features were maintained after the cryogenic cleaning process. Also, the thicknesses of the dielectric contact layer were also measured using conventional ellipsometric measurements to determine if the thickness of the dielectric contact layer was maintained. In both cases, the resolution of the measurements was approximately 5 nm. No changes in feature dimensions or dielectric contact thicknesses were detected after to the cryogenic cleaning process. Additionally, the physical and chemical properties of the dielectric contact and other exposed films on the substrates were also generally unaffected, as no modifications of subsequent processing steps were required.
The microelectronic workpieces discussed herein can include various elements therein and/or layers thereon. These can include barrier layers, other dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the invention can be used in a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention can have been disclosed with respect to only one of several implementations, such feature can be combined with one or more other features of the other implementations as can be desired and advantageous for any given or particular application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the following claims.
