Patent Application
20130108779
1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of filing voids in copper conductive structures on integrated circuit devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of field effect transistors (NMOS and PMOS transistors) that substantially determine performance of the integrated circuits. Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the transistors and the overall functionality of the circuit. Given that the channel length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of additional techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of highly-conductive copper lines and vias to provide electrical wiring connections to the transistors, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors).
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, as the device dimensions have decreased, the physical size of the conductive interconnections, e.g., metal lines and metal vias formed in multiple metallization layers about the device level, have also become smaller. Accordingly, the electrical resistance of conductive interconnections becomes a significant issue in the design of the overall product. Moreover, the reduction in size of the conductive interconnections makes it more difficult to manufacture copper conductive lines and vias without introducing an unacceptable level of voids in the resulting structure.
One illustrative example of the methods employed to form the copper conductive line 100 depicted in
However, given the small size of conductive lines and via on modern semiconductor devices, it is sometimes difficult to manufacture such conductive structures without forming voids in the final structure. Problems such as misalignment due to photolithography errors, undersized openings 11 due to etching problems and incomplete cleaning operations all may lead to the formation of voids in the final conductive structures.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming copper conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a conductive copper structure in a layer of insulating material and performing an electroless deposition to selectively form a fill layer comprised of a conductive material on the copper containing structure, the fill layer being adapted to at least partially fill any voids that may exist in the conductive copper structure.
In another illustrative example, a method disclosed herein includes the steps of forming a conductive copper structure in a layer of insulating material, performing an anneal process at a temperature within the range of 80-350° C. on the conductive copper structure and, after performing the anneal process, performing an electroless deposition process to selectively form a fill layer comprised of a conductive material on the copper containing structure, wherein the fill layer has a thickness in the range of 2-10 nm and wherein the fill layer is adapted to at least partially fill any voids that may exist in the conductive copper structure.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming filing voids in copper conductive structures on integrated circuit devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to
The fill layer 202 may be formed by performing a selective formation process, i.e., a non-blanket deposition process, to selectively form a conductive material on the copper containing structure 200. For example, an electroless plating or a selective deposition process may be performed so at to selectively form cobalt on, for example, copper, tantalum, or tantalum nitride, or combinations thereof. In one illustrative embodiment, the fill layer 202 may be comprised of a variety of materials such as a cobalt-tungsten-phosphorus (CoWP) material wherein the cobalt will act to inhibit the migration of copper from the conductive copper structure 200. The thickness of the fill layer 202 on the flat upper surface of the bulk copper region 20 may range from approximately 2-10 nm. In one example, the fill layer 202 may be formed at any time after performing the basic post-anneal process, e.g., at a temperature of 80-350° C., on the conductive copper structure 200.
The techniques described herein may help to at least reduce or perhaps eliminate one or more of the problems identified in the background section of the application. For example, in the case where the fill layer 202 comprises a barrier metal, the fill layer 202 may act to restrain undesirable copper migration. The fill layer 202 may also act to further prevent the increase in the size of the voids within the conductive structure. In the case where the void has degraded or destroyed part of the barrier layer 14 and/or the barrier layer 16, the fill layer 202 may act to restore the functionality of the lost barrier material, thereby reducing the chance of undesirable copper migration.
The basic components of the conductive copper structure 200 may be formed in a manner similar to those corresponding structures and layers depicted for the copper conductive line 100 shown in
In forming the conductive copper structure 200, an opening or trench 11 is etched into the layer of insulating material 10 using known photolithography and etching techniques. Thereafter the barrier layer 14, 16 are conformably deposited in the opening 11 by performing, for example, a conformal plasma-enhanced physical vapor deposition (PEPVD) process. The barrier layers 14, 16 may be comprised of a variety of different materials and the thickness of such layers may vary. In one illustrative embodiment, the barrier layers 14, 16 are comprised of tantalum nitride (TaN) and tantalum (Ta), respectively, and they each may have a thickness of about 1-5 nm. The copper seed layer 18 may then be blanked deposited above the layer of insulating material 10 and in the opening 11 by performing a conformal PEPVD process. The copper seed layer 18 may have a thickness that ranges from about 1-5 nm. Thereafter, in one embodiment, a well-known electroplating process is performed to deposit bulk copper material 20 in the opening 11 and across the device. In general, during the electroplating process, a voltage is applied to the copper seed layer 18 such that it attracts copper ions that are in the copper plating solution. After the bulk copper is deposited, a CMP process is performed to remove the excess material positioned outside of the opening 11. It should be noted that, although the copper seed layer 18 is depicted in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
