Patent Application
20180366562
The present disclosure relates to integrated circuit structures, and more particularly, to methods of forming an integrated circuit structure including a notch within a fin that is filled with a rare earth oxide and a related integrated circuit structure.
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, electric current from the source to the drain can be turned on and off. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET structure is a “FINFET.” which may be formed upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FINFET can include a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting as a drain terminal. A gate structure, typically composed of polysilicon and/or a metal, can be formed around one or more of the semiconductor fins. By applying a voltage to the gate structure, an electrically conductive channel can be created between the source and drain terminals of each fin in contact with the gate.
In some cases, a FINFET may be desirable in IC structures which do not include an SOI layer with a corresponding buried insulator layer. For example, processors for mobile applications can include forming transistor structures on a bulk substrate instead of an SOI-type structure. Planar devices can be formed conventionally within the bulk substrate without substantial modifications. A FINFET may also be adapted for use on a bulk substrate material instead of SOI. However, FINFETs on bulk substrates can have a leakage path in the sub-fin region, i.e., the region of the fin below the gate. This leads to significant drain to source current, i.e., punch-through current, which has to be suppressed with a punch-through stop implant. A punch-though stop implant includes implanting dopants to prevent expansion of the drain depletion into the source terminal. However, such implanting leads to unwanted high doping concentrations in the fin which degrades carrier mobility and introduces within-fin non-uniformities.
A first aspect of the disclosure is directed to a method for forming an integrated circuit structure. The method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.
A second aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: forming a fin from a substrate such that the fin is disposed over a remaining portion of the substrate; forming a gate structure perpendicular to and substantially surrounding the fin such that a channel region is defined beneath the gate structure within the fin; removing a portion of the fin that is adjacent to the channel region from opposing sides of the channel region such that the channel region remains disposed beneath the gate structure; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) to substantially fill the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.
A third aspect of the disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a fin over a substrate; a gate structure perpendicular to and substantially surrounding the fin, the gate structure defining a channel region thereunder within the fin; a source region and a drain region over the fin on opposing sides of the channel region; and a rare-earth oxide (REO) disposed between the source region and fin, and between the drain region and the fin, the REO being partially disposed beneath the channel region within the fin.
The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.
The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
The present disclosure relates to integrated circuit structures, and more particularly, to methods of forming an integrated circuit structure including a notch within a fin that is filled with a rare earth oxide and a related integrated circuit structure. Aspects of the disclosure described herein reduce punch through current and provide a means for isolating the source region and drain region from the substrate.
Referring now to
Fins 110 may be formed from substrate 102, e.g., by patterning a mask and etching, such that fin overlies a remaining portion of substrate 102. Where substrate 102 includes an SOI substrate, fins 110 may be formed from the upper semiconductor layer over the insulator layer. As used herein “etching” generally refers to the removal of material from a substrate or structures formed on the substrate by wet or dry chemical means. In some instances, it may be desirable to selectively remove material from certain areas of the substrate. In such an instance, a mask may be used to prevent the removal of material from certain areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etching may be used to selectively dissolve a given material and leave another material relatively intact. Wet etching is typically performed with a solvent, such as an acid. Dry etching may be performed using a plasma which may produce energetic free radicals, or species neutrally charged, that react or impinge at the surface of the wafer. Neutral particles may attack the wafer from all angles, and thus, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases from a single direction, and thus, this process is highly anisotropic. A reactive-ion etch (RIE) operates under conditions intermediate between sputter etching and plasma etching and may be used to produce deep, narrow features, such as trenches. While one fin 110 is shown, it is to be understood that any number of fins may be employed without departing from aspects of the disclosure.
IC structure 100 may also include an isolation region (not shown) over substrate 102 to separate device regions (not individually referenced).
Still referring to
Where gate structure 120 includes a dummy gate structure, gate structure 120 may be formed within IC structure 100 such that dummy gate structure 120 is perpendicular to and overlaps fin 110. Dummy gate structure 120 may be formed by depositing and etching a dummy gate material, e.g., amorphous carbon, over IC structure 100 including fin 110 such that a dummy gate 122 remains. While not shown, the formation of dummy gate 122 may be preceded by the formation of a gate dielectric material as known in the art. After dummy gate 122 is formed, a spacer material (e.g., silicon oxide, silicon nitride) may be deposited over IC structure 100 including fin 110 and etched such that spacers 124 remain on opposing sides of dummy gate 122, thereby forming dummy gate structure 120.
Where gate structure 120 includes an active gate structure, gate structure 120 may be formed within IC structure 100 such that active gate structure 120 is perpendicular to and overlaps fin 110. Active gate structure 120 may be formed by depositing and etching active gate materials, e.g., a gate conductor 126, in a gate-first process. Subsequently, spacers 124 may be formed on opposing sides of gate structure 120 such that spacers 124 remain on opposing sides of active gate structure 120. However, in a gate-last process, active gate structure 120 may be formed after the forming of the source region and the drain region as will be described herein. In a gate-last process, a dummy gate, e.g., dummy gate 122, may be first formed over fin 110 as described above, and removed from between spacers 124 after the source region and the drain region are formed. Subsequently, active gate structure 120 may be formed between spacers 124 by forming the active gate materials therebetween. In such an embodiment, active gate structure 120 may be known as a replacement metal gate. Further, where gate structure 120 is an active gate structure, a gate cap layer 128 (e.g., silicon nitride, silicon oxide) may be formed (e.g., deposition, patterning a mask thereover and etching) over gate conductor 126 as shown in phantom.
In either embodiment, the active gate materials may include, for example, a gate conductor 126. Gate conductor 126 may include, for example, at least one of: titanium, titanium nitride, tungsten, tungsten nitride, copper, copper nitride, tantalum, tantalum nitride, alloys or combinations thereof. While not shown, it is to be understood that active gate structure 120 may also include other conventional active gate stack layers beneath gate conductor 126, for example, a layer having a high dielectric constant (high-k) layer, barrier layers, wetting layers, and work function metal layers. High-k layers may include a material having a dielectric constant greater than 4.0 such as, for example, at least one of: hafnium oxide, hafnium silicate, nitride hafnium silicate, zirconium oxide, zirconium silicate, titanium oxide, lanthanum oxide, yttrium oxide, aluminum oxide, or combinations thereof. Barrier and/or wetting layers may include, for example, titanium nitride. Work function metal layers may each act as a doping source, and a different work function setting metal can then be employed depending on whether a n-type field-effect-transistor (NFET) or a p-type field-effect-transistor (PFET) device is desired. Thus, the same gate conductor (gate conductor 126) can be used in each of the devices, yet a different (if so desired) work function setting metal can be used in one or more devices to obtain a different doping polarity. By way of example only, suitable work function setting metals for use in PFET devices include, but are not limited to: aluminum, dysprosium, gadolinium, and ytterbium. Suitable work function setting metals for use in NFET devices include, but are not limited to: lanthanum, titanium, and tantalum. In such embodiments, conductor 126 may be formed over the work function metal layers.
In either embodiment, i.e., whether gate structure 120 is a dummy gate structure or an active gate structure, a channel region 130 may be defined beneath gate structure 120 within fin 110. Turning now to
Turning now to
Turning now to
REO 142 may include, for example, at least one of or a compound of: cerium oxide, dysprosium oxide, erbium oxide, europium oxide, gadolinium oxide, holmium oxide, lanthanum oxide, lutetium oxide, neodymium oxide, praseodymium oxide, promethium oxide, samarium oxide, scandium oxide, terbium oxide, thulium oxide ytterbium oxide, or yttrium oxide. In some embodiments, REO 142 includes a material that has a lattice orientation that matches a lattice orientation of substrate 102, and therefore, fin 110. That is, REO 142 may be customized such that REO 142 includes a lattice that is matched to the lattice of substrate 102. For example, REO 142 may include a compound of two materials selected from the list of REO materials. In this example, the first material (A) may have a lattice that is larger than the lattice of substrate 102, and the second material (B) may have a lattice that is smaller than the lattice of substrate 102. In order to make a compound of materials AB, e.g., AxBy, the ratio of A to B, or the values of x and y in this example, may be optimized to obtain an REO compound having a lattice that is substantially similar to the lattice of substrate 102.
After REO 142 is formed, sacrificial spacer 134 may be removed and source region 146 and drain region 148 are each formed over REO 142 that is disposed over fin 110 on opposing sides of channel region 130 to provide a resulting IC structure 190 as shown in
As shown in
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s). “Substantially” refers to largely, for the most part, entirely specified or any slight deviation which provides the same technical benefits of the disclosure.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
