Patent Application
20230420575
The present disclosure relates to semiconductor devices. In particular, the disclosure relates to silicon carbide semiconductor devices having implanted regions.
Power electronic devices manufactured using silicon carbide (SiC) are capable of high blocking voltages. For power devices having blocking voltages in the 600V-1000V range, SiC junction field effect transistors (JFETs) have two to three times smaller chip area than SiC metal-oxide semiconductor field effect transistors (MOSFETs). SiC JFETs can also be manufactured with a simpler manufacturing process than MOSFETs, which can lead to lower manufacturing costs. Moreover, SiC JFET devices have no SiO2—SiC interface, which may increase device reliability, as oxide layers may break down under high voltage operation. JFET devices have the drawback of being normally-on devices. However, their advantages may outweigh their disadvantages in power applications, such as high reliability Si—SiC heterogeneously integrated circuits.
A method of forming a buried implanted region in a silicon carbide semiconductor layer according to some embodiments includes implanting first dopant ions having a first conductivity type into the silicon carbide semiconductor layer along a first axis at a first dose and first implant energy to form a first channelized doping profile. The first channelized doping profile has a first de-channeled peak at a first depth in the silicon carbide semiconductor layer and a first channeled peak at a second depth in the silicon carbide semiconductor layer that is greater than the first depth. The method further includes implanting second dopant ions having the first conductivity type into the silicon carbide semiconductor layer along the first axis at a second dose and second implant energy to form a second channelized doping profile. The second channelized doping profile has a second channeled peak at a third depth in the silicon carbide semiconductor layer that is between the first depth and the second depth. The first channelized doping profile and the second channelized doping profile form a combined doping profile that defines the buried implanted region.
The method may further include annealing the silicon carbide semiconductor layer after implanting the first and/or second dopant ions to activate the first and second dopant ions.
The first dose may be selected to form the de-channeled peak in the silicon carbide semiconductor layer at the first depth when implanted at the first implant energy.
Implanting the first dopant ions and/or implanting the second dopant ions may be performed at room temperature. In some embodiments, implanting the first dopant ions and/or implanting the second dopant ions is performed at a temperature that is lower than room temperature.
In some embodiments, the combined doping profile has a variation in doping concentration between the de-channeled peak and the channeled peak of less than about 15%. In some embodiments, the combined doping profile has a variation in doping concentration between the de-channeled peak and the channeled peak between about 5% and about 10%, and in some embodiments, the combined doping profile has a variation in doping concentration between the de-channeled peak and the channeled peak of about 5%.
The buried implanted region may be a channel region of a vertical semiconductor device, such as a vertical junction field effect transistor device, or a current spreading layer of a semiconductor device.
The buried implanted region may have a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0 E17 atoms/(cm3-micron), and in some embodiments greater than about 1.2 E17 atoms/(cm3-micron).
The first depth may be less than about 1.5 microns and the second depth may be greater than about 2 microns. A distance between the first depth and the second depth may be greater than about 1 micron.
The first implant dose and the second implant dose may each be less than about 1E13/cm2. In some embodiments, the first implant energy is greater than the second implant energy.
A silicon carbide semiconductor layer according to some embodiments includes a buried implanted region that is buried in the silicon carbide layer at a first depth from a surface of the silicon carbide layer, the buried implanted region defined by an implant doping profile having a first thickness between the first depth and a second depth, wherein the second depth is greater than the first depth. The buried implanted region may have a variation in doping concentration between the de-channeled peak and the channeled peak of less than about 15%.
A silicon carbide semiconductor layer according to some embodiments includes a buried implanted region that is buried in the silicon carbide layer at a first depth from a surface of the silicon carbide layer, the buried implanted region defined by an implant doping profile having a first thickness between the first depth and a second depth, wherein the second depth is greater than the first depth. The buried implanted region has a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0E17 atoms/(cm3-micron).
The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and together with the detailed description serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and the various ways in which it may be practiced. In the drawings:
Embodiments of the inventive concepts are explained more fully with reference to the non-limiting aspects and examples that are described and/or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and features of some embodiments may be employed with other aspects as the skilled artisan would recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as to not unnecessarily obscure the aspects of the disclosure. The examples used herein are intended merely to facilitate an understanding of ways in which the disclosure may be practiced and to further enable those of skill in the art to practice the aspects of the disclosure. Accordingly, the examples and aspects herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Moreover, it is noted that like reference numerals represent similar parts throughout the several views of the drawings.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the another element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art.
Although a JFET device is sometimes referred to as a static induction transistor, the term JFET will be used in the description below. However, it will be appreciated that embodiments described herein may be applied to any device that uses a depletion region to modulate the conductivity of a channel in a mesa.
Although some embodiments are described in the context of a silicon carbide JFET device, it will be appreciated that aspects of the inventive concepts may be applicable to other types of devices, such as MOSFETs, insulated gate bipolar transistors (IGBTs) and other types of devices.
An n-channel vertical JFET structure 10 is shown in
A p+ gate region 18 is provided as part of the mesa 12 adjacent the channel region 24. A p++ gate contact region 32 is provided adjacent the gate region 18.
The vertical JFET unit cell structure 10 is symmetrical about the axis 30 and includes two gate regions 18 as part of the mesa 12 on opposite sides of the channel region 24.
The channel of the vertical JFET structure 10 is formed within the mesa 12. The channel width is into the plane of
In operation, conductivity between the source layer 16 and the drain layer 26 is modulated by applying a reverse bias to the gate region 18 relative to the source layer 16. To switch off an n-channel device such as the JFET structure 10, a negative gate-to-source voltage, or simply gate voltage (VGS) is applied to the gate region 18. When no voltage is applied to the gate region 18, charge carriers can flow freely from the source layer 16 through the channel region 24 and the drift layer 15 to the drain layer 26.
In a JFET device such as the JFET device 10 shown in
Dopant concentration in the channel is an important parameter of a JFET device, as it affects the relationship between gate bias and threshold voltage. A substantially constant, predictable channel doping is thus preferable to have low on-resistance and low off-state leakage.
In a vertical SiC n-channel JFET structure 10 as shown in
The JFET channel region 24 is adjacent the gate region 18 between the n+ transition region 16 and the drift layer 15. To behave as a long-channel MOSFET without drain-induced barrier lowering (DIBL), the JFET channel 24 typically is 1-2 um long, which for a vertical channel device would be 1-2 um deep in the structure. Thus, the channel region extends from a depth of about 1 micron below the top surface 10A of the structure to a depth of 2.5 to 3 microns below the surface 10A. The JFET channel 24 can be doped epitaxially. However, doping variation in SiC epitaxy can be up to 20%, which would introduce a 20% variation in channel doping (Nch) in equation [1] below for threshold voltage (VT).
The threshold voltage VT of a vertical SiC JFET device is given by equation [1], in which Vbi is the built-in voltage of the P-N junction between the gate region 18 and the channel region 24, Nch is the doping concentration of the channel region 24, q is the charge of an electron, Vbarrier is the potential barrier in the channel at which VT is defined, W is the half-channel depth (i.e., the depth of the channel to from the gate region 18 to the centerline 30 of the structure), and £ is the permittivity of silicon carbide.
Equation [2] relates the change in threshold voltage (dVT) to change in channel doping (dNch).
With typical values of Nch=5E16/cm3, half-channel depth (W)=0.33 microns, electron charge (q), Vbi in SiC of about 3V, and the potential barrier in the channel at which VT is defined (Vbarrier) of about −2V, the threshold voltage VT is centered at −3.95V. With a 20% variation of Nch, VT varies between −5.45V and −4.46V, which is a spread of about 1V. Such a variation might be acceptable in some applications but not in others. In addition to Nch, VT also varies with channel depth W, which for a trench JFET is very sensitive to the width of the mesa. In order to reduce this sensitivity, there is a floor on how low W can be reduced while also not increasing on-state resistance significantly. However, equation [2] shows that sensitivity of VT to Nch is proportional to W2, which means that sensitivity cannot be reduced without impacting on-state resistance negatively. As a corollary, equation [2] also shows that if variation in N ch can be reduced, then W can be increased while keeping the same variation in VT. In addition to variation of VT with Nch, a typical 0.2 um variation in mesa width due to process imprecision leads to a 0.2 micron variation in W, which with the same typical values as cited above can lead to approximately a 3V variation in VT between −6.56V and −3.56V. Thus, more precise control of Nch can remove one important factor in variation of VT in a JFET.
A JFET channel is typically formed either using epitaxy or random implants. Doping during epitaxial growth may suffer from inherent variability (e.g., 20% typically in SiC). Random (non-channeled) implantation of dopant ions in silicon carbide may be limited to depths of up to about 0.5 to 1 micron without using impractically high implant energies, which can have very low beam current and hence little throughput. Moreover, the use of high implant energies can cause significant undesirable lattice damage to the silicon carbide layer, which must be annealed at high temperatures to repair. Channel regions for vertical channel JFETs may need to be about 1 to 3 microns deep, and should preferably be doped uniformly and with little variation. It may be difficult to satisfy these requirements using epitaxial doping or random implants.
Some embodiments described herein utilize channeled implants to form a buried region in a silicon carbide layer, such as a channel region of a vertical JFET device. In particular embodiments, ions may be implanted substantially parallel to a <0001>, <11-20> or <11-23> axis of a silicon carbide layer to obtain channeled implants. Multiple channeled implants may be performed to obtain a doped buried layer that has a substantially uniform doping profile as a function of depth within the silicon carbide layer. For example, in some embodiments, multiple successive implantations may be performed at different energies and/or doses form a substantially uniformly doped JFET channel region 24 between depth of 1 micron and 2.5-3 microns below the surface 10A. The implantations may be performed at a maximum implantation energy of 1.8 MeV and a total dopant ion dose that stays below an upper limit above which significant de-channeling of the dopant concentration/range starts.
Channeling of implants may occur when ions are implanted parallel or nearly parallel to a crystal axis of a semiconductor layer so that there is a lower likelihood of the implanted ion colliding with the crystal lattice of the semiconductor layer the surface of the semiconductor layer compared to implantation at a random angle relative to the crystal lattice. Channeled implants may therefore penetrate much deeper into the semiconductor layer than random implants.
As can be seen in
When ions are implanted along the <0001> axis of a hexagonal silicon carbide polytype (such as 2H, 4H or 6H), the resulting doping profile may exhibit a so-called “de-channeled” peak near the surface of the silicon carbide layer depending on the dose of the implant. A de-channeled peak refers to a peak in the implanted doping concentration that is formed as a result of implanted ions colliding with the crystal lattice of the silicon carbide layer near the surface of the layer rather than channeling deeply in to the semiconductor layer. When the implant dose is increased, the likelihood of de-channeling of ions occurring increases. For example,
In particular,
As can be seen in
As seen in the doping profile 402, at an implant dose of 1E13/cm2, a de-channeled peak 422 is just beginning to form in the doping profile. However, it is slightly lower than the channeled peak 412. Similarly, in the doping profile 401, the de-channeled peak 422 is even less pronounced compared to the channeled peak 411.
With 1.5 MeV implants channeled along the <0001> crystallographic axis as shown in
Some embodiments described herein use the presence of a de-channeled peak in a channeled implant profile to help form a highly uniform buried implanted region in a silicon carbide layer by combining multiple successive implants to form a combined implant profile.
The second implantation is performed at a high enough energy to form a second channeled implant peak 526 at a depth d3 that is between d1 and d2, but at a low enough dose so as not to form a significant de-channeled peak. To place the second channeled peak shallower than the first channeled peak, the second implantation may be performed at a lower implant energy than the first implant. That is, the second channeled implant can be used to fill in the valley between the channeled and de-channeled peaks 514, 516 to form a substantially uniform doping profile.
The first depth d1 may be less than about 1.5 microns, and the second depth d2 may be greater than about 2 microns. The distance from d1 to d2 may be greater than about 1 micron.
Some embodiments use chained (i.e., sequential) channeled implants with a maximum energy of 1.8 MeV to 2 MeV and a combined dose no more than about 1.5E13/cm2 to form a buried region in a silicon carbide layer that has less than about 5% variation in doping concentration along the channel length and less than about 5% variation in doping concentration between structures across a wafer (e.g., across a 200 mm SiC wafer). For a JFET structure, the buried region may be a channel region or channel layer. The balance achieved between the channeled and de-channeled peaks of the implants may enable substantially uniform doping along the length of the vertical channel of the JFET (i.e., depth into the mesa), as well as in multiple devices across a wafer.
In some embodiments, by appropriately selecting the implant conditions of the first and second implantations, a buried doped region, defined as the region between the de-channeled peak 514 and the first channeled peak 516, may be formed in a semiconductor having a variation of doping concentration of less than about 15%. In some embodiments, the variation of doping concentration in the buried doped region may be from about 5% to about 10%, and in some embodiments, the variation of doping concentration in the buried doped region may be about 5%.
Moreover, because of the nature of channeled implants, the doping concentration of the buried doped region may have a very sharp gradient, or drop-off, at the bottom of the region. For example, in some embodiments, the buried implanted region has a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0E17 atoms/(cm3-micron), in some embodiments at a rate of greater than about 1.2E17 atoms/(cm3-micron). In some embodiments, the buried implanted region has a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0E17 atoms/(cm3-micron) and less than 1.5E17 atoms/(cm3-micron).
A third doping profile 606 is formed by a first implantation at an energy of 1.8 MeV and a dose of 8E12/cm2 and a second implantation at an energy of 1.2 MeV and a dose of 3E12/cm2. The third doping profile is highly uniform at about 6 E16/cm3 to 7E16/cm3 over the depth of the implanted region from about 1.25 microns to about 2.7 microns.
Referring to
Brief reference is made to
Thus, the epitaxial layers 65 of the silicon carbide layer 15 may not be parallel to the top surface 15A of the silicon carbide layer, but rather may be tilted at an angle corresponding to the off-axis angle at which the silicon carbide layer was formed.
To perform channeled ion implantation, the stage 120 may be tilted by an angle θ that is equal to the off-axis angle so that the ions 125 are implanted parallel to the <0001> crystallographic axis of the silicon carbide layer 15.
Referring again to
The buried implanted region may have a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0E17 atoms/(cm3-micron), and in some embodiments at a rate of greater than about 1.2E17 atoms/(cm3-micron). In some embodiments, the buried implanted region has a dopant concentration tail beneath the buried implanted region that decreases at a rate of greater than about 1.0E17 atoms/(cm3-micron) and less than 1.5E17 atoms/(cm3-micron).
The first depth may be less than about 1.5 microns and the second depth may be greater than about 2 microns. The distance between the first depth and the second depth may be greater than about 1 micron.
The first implant dose and the second implant dose may each be less than about 1E13/cm2, and may have a combined dose of about 1.5E13/cm2 or less.
The first implant energy may be greater than the second implant energy.
The method may further include annealing the silicon carbide semiconductor layer after implanting the first and second dopant ions to activate the first and second dopant ions.
In some embodiments, the first dose may be selected to form the de-channeled peak in the silicon carbide semiconductor layer at the first depth when implanted at the first implant energy.
In some embodiments, implanting the first dopant ions and/or implanting the second dopant ions may be performed at room temperature or at a temperature that may be lower than room temperature.
The combined doping profile may have a variation in doping concentration between the de-channeled peak and the channeled peak of less than about 15%.
In some embodiments, the combined doping profile may have a variation in doping concentration between the de-channeled peak and the channeled peak between about 5% and about 10%, and in some embodiments, the combined doping profile may have a variation in doping concentration between the de-channeled peak and the channeled peak of about 5%.
The buried implanted region may be a channel region of a vertical semiconductor device, such as a vertical junction field effect transistor device. In some embodiments, the buried implanted region may be a current spreading layer of a semiconductor device.
Some embodiments provide a silicon carbide semiconductor layer having a buried implanted region that is buried in the silicon carbide layer at a first depth from a surface of the silicon carbide layer. The buried implanted region is defined by an implant doping profile having a first thickness between the first depth and a second depth, wherein the second depth is greater than the first depth. The buried implanted region has a variation in doping concentration between the de-channeled peak and the channeled peak of less than about 15%.
As noted above, a JFET channel is typically formed either using epitaxy or random implants. However, it may be difficult to achieve the required depth and/or thickness of a buried region or the required doping uniformity using either epitaxial doping or random implantation.
As discussed above, using chained channeled implants into SiC at room or lower temperatures, deep and uniformly doped regions can be obtained. An advantage of using chained channeled implants to form the channel of the vertical JFET is that the channel region can have a substantially uniform dopant concentration both along the channel length of an individual JFET cell, and between JFET cells and JFET devices across a large wafer area. Additionally, channeled implants may have a more abrupt implant tail, which allows the implant to be confined better in the desired JFET channel, in contrast to random implants in SiC which have deep tails that encroach into the drift region of the device and may worsen the trade-off between device parameters.
Some advantages of this invention maybe quantified by considering three scenarios, namely, (1) a JFET channel doped at 5E16/cm3 that is 1.7 microns long, grown epitaxially with a 20% variation (+1-10%), (2) a JFET channel doped at 5E16/cm3 and only 0.5 microns deep, formed with random implants (channel length is limited because implant energy is limited to 1.8 keV, which gives an implant up to 1.5 microns deep, and the source region consumes 1 micron, leaving 0.5 microns length of channel), and (3) a JFET channel 5E16 doped, 1.7 microns long, formed using 1.8 MeV+1.2 MeV chained channeled implants that extend 2.7 microns deep along the <0001> direction, which gives an implanted region up to 2.7 microns deep. The source region consumes 1 micron, leaving 1.7 microns of channel length.
With a process variation of 0.2 microns in mesa width, the results are tabulated in Table 1.
As seen in Table 1, using epitaxially grown channel leads to a delta VT of 1.2V (range between −2.2V and −1V) under the given process variation. The delta VT can be reduced to 0.9V, i.e. a reduction of 25%, by using an implanted channel. However, using random implants, the channel length can only be up to 0.5 microns in length, which is a short-channel device that may experience significant DIBL at high drain voltages. With a 750V rated drift region, such a device can only block <400V, which is not sufficient for a 400V rail application. Using channeled implants, VT variation can be restricted, while also maintaining the channel length required to not experience DIBL.
In addition to the reduction variation in VT, forming an implanted channel region may also reduce the maximum specific on-resistance of the device by up to about 4%.
A JFET device as described herein may also be advantageously used for other SiC JFET applications such as in a solid-state circuit breaker as a normally-on SiC JFET switch.
Although embodiments of the inventive concepts have been described in considerable detail with reference to certain configurations thereof, other versions are possible. The field plates and gates can also have many different shapes and can be connected to the source contact in many different ways. Accordingly, the spirit and scope of the invention should not be limited to the specific embodiments described above.
