Patent Application
20060084248
The present invention generally relates to the field of microelectronic devices, and more particularly to methods of optimizing implantation conditions while minimizing channeling effects.
Integrated circuits form the basis for many electronic systems. An integrated circuit may include a vast number of transistors and other circuit elements that may be formed on a single semiconductor wafer or chip and may be interconnected to implement a desired function. Transistors may comprise active areas, such as a gate, a source and/or a drain, which are electrically conductive areas within the transistor, as are well known in the art.
As transistor dimensions are increasingly scaled down, the thickness 612 of the active area 602 can become comparable and/or smaller than a penetration depth 614 of the implant species 611 of the amorphizing implant 610. Consequently, the amorphizing implant may penetrate through the active area 602 and into underlying regions of the transistor, such a gate oxide region 604 and/or a channel region 606.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
a-1d represent methods of forming structures according to an embodiment of the present invention.
a-4b represent structures according to another embodiment of the present invention.
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Methods and associated structures of forming a microelectronic device are described. Those methods comprise implanting a first concentration of a species into an active area with a first energy, wherein the species pre-damages a portion of the active area, and then implanting a second concentration of the species into the active area with a second energy, wherein the total concentration of the species does not substantially penetrate an underlying channel region. By utilizing a first energy which is lower than the second energy, the range of the first implant may be shallower than the range of the second implant. In this manner, the deleterious channeling effects may be substantially reduced and/or eliminated. Thus, improved device performance, as well as decreased active area thickness, may be achieved.
a-1d illustrate an embodiment of a method of forming a microelectronic structure, such as a transistor structure, for example.
The microelectronic structure 100 may further comprise an oxide region 104, for example in the case when the active area 102 comprises a gate, the oxide region 104 may comprise a gate oxide, as is known in the art. The gate oxide may comprise a thickness below about 30 angstroms, for example, and may comprise silicon dioxide. The microelectronic structure 100 may further comprise an underlying channel region 106, wherein electrical current may flow, as is known in the art. The microelectronic structure 100 may also comprise a substrate region 108, which may comprise silicon, silicon-on-insulator, silicon on diamond, or combinations thereof, by illustration and not limitation.
A first amorphizing implant 110 may be applied to the microelectronic structure 100 utilizing various process tools as are well known in the art (
The first amorphizing implant 110 may comprise a first energy and a first dose of the species 111. The magnitude of the first energy and the first dose of the first amorphizing implant 110 may be chosen such that the first energy and the first dose of the first amorphizing implant 110 may determine a first penetration depth 114 of the implant species 111. The first penetration depth 114 may comprise the depth, or distance, that the species 111 of the first amorphization implant 110 may penetrate into the active area 102. In other words, one skilled in the art will recognize that the first penetration depth 114 may comprise the implant tail of the implant species 111 as implanted into the active area 102.
In one embodiment, the first dose may range from about 6 keV to about 8 keV, with an implant species comprising germanium. The first dose may range from about 6E14 to about 8E14, with a first penetration depth 114 comprising about 600 angstroms. The implantation of the species 111 into the active area 102 with the first energy and first dose may introduce a first concentration of the implant species 111 into the active area. In one embodiment, the first concentration of the species 111 may generally be less than that required to achieve a desired amount of amorphization of the active area 102, thus a second amorphizing implant 116 (
The first penetration depth 114 of the first amorphizing implant 110 into the active area 102 may serve to control a final penetration depth 118 of the second amorphizing implant 116 into the active area 102. That is, because the first amorphizing implant 110 may pre-damage the active area 102, the second amorphizing implant 116 is blocked in a sense, from penetrating substantially further into the active area 102 than the first penetration depth 114. Thus the channeling effect, i.e., the penetration from the second amorphizing implant 116 of the species 111 beyond the active area depth 112 into the oxide region 104 and/or underlying channel region 106 may be significantly reduced and/or eliminated by the pre-damage from the first amorphizing implant 110. In one embodiment, the ratio of the final penetration depth 118 to the active area depth 112 may be less than about 2 to 3 (2:3).
The second amorphizing implant 116 may comprise a second energy and a second dose. In one embodiment the second energy may range from about 13 keV to about 17 keV, but may be of greater magnitude than the first energy. The second dose may range from about 3E14 to about 7E14, but may be of greater magnitude than the first dose of the first amorphizing implant 110. The second amorphizing implant 116 of the species 111 may introduce a second concentration of the species 111 into the active area 102.
A total concentration 120 of the species 111 (which represents the combined amount of species 111 implanted from the first amorphizing implant 110 and the second amorphizing implant 116) may be chosen, by varying the amount of the first and second implant doses and energies such that the total concentration 120 of the implant species 111 achieves the desired amount, or depth, of amorphization within the active area 102. Thus, by utilizing a first amorphizing implant 110 combined with a second amorphizing implant 116, wherein the initial amorphizing implant 110 is at a lower energy and dose than the second amorphizing implant 116, a desired total concentration of implant species 111 may be achieved. In one embodiment, a desired amorphizing depth may be achieved which may result in a shallower final penetration depth 118 than if simply one implant (applied at the dose and energy to achieve the desired total concentration) had been applied to the active area 102.
In another embodiment (
In one embodiment, the third penetration depth 218, which may represent the highest energy amorphizing implant, may comprise the longest penetration depth amongst the first, second and third penetration depths 214, 216, 218. Because the first penetration depth 214 of the first amorphizing implant effectively reduces and/or blocks the channeling effect of the second and third amorphizing implants, the third penetration depth 218 is substantially less than the active area depth 212.
In one embodiment, the ratio of the third penetration depth 218 to the active area depth 212 may be less than about 2 to 3 (2:3). Thus, by utilizing multiple amorphizing implants, wherein the initial amorphizing implant is at a lower energy and dose than successive amorphizing implants, a desired total concentration of implant species and a desired amorphizing depth may be achieved, without incurring the deleterious channeling effects of the species 211. In one embodiment, a desired amorphizing depth may be achieved which may result in a shallower final penetration depth (after successive implants are applied) than if simply one implant (applied at the dose and energy to achieve the desired total concentration) had been applied to the active area 202. Consequently, transistor device performance, such as a higher drive current, may be greatly enhanced, in some embodiments.
a depicts structures that may be formed in accordance with another embodiment of the present invention. A microelectronic structure 400, such as a transistor structure, may comprise active areas 402a, 402b, 402c, which may in one embodiment comprise a gate, a source and a drain respectively. The active areas 402a, 402b and 402c may comprise active area depths 412a, 412b, and 412c respectively. The microelectronic structure 400 may further comprise a gate oxide 404 and a channel region 406, as are well known in the art. The microelectronic structure 400 may include a species 411 such as germanium, arsenic, boron and/or silicon or combinations thereof, which may be implanted during an amorphizing implant (not shown). The species 411 may penetrate into the active areas 402a, 402b, 402c corresponding to the penetration depths 414a, 414b, 414c.
A silicidation process may be performed on the microelectronic structure 400, as is well known in the art (
In the system 500, a microelectronic structure 503 may be communicatively coupled to a printed circuit board (PCB) 501 by way of an I/O bus 508. The communicative coupling of the microelectronic structure 503 may be established by physical means, such as through the use of a package and/or a socket connection to mount the microelectronic structure 503 to the PCB 501 (for example by the use of a chip package and/or a land grid array socket). The microelectronic structure 503 may also be communicatively coupled to the PCB 501 through various wireless means (for example, without the use of a physical connection to the PCB), as are well known in the art.
The system 500 may include a computing device 502, such as a processor, and a cache memory 504 communicatively coupled to each other through a processor bus 505. The processor bus 505 and the I/O bus 508 may be bridged by a host bridge 506. Communicatively coupled to the I/O bus 508 and also to the microelectronic structure 503 may be a main memory 512. Examples of the main memory 512 may include, but are not limited to, static random access memory (SRAM) and/or dynamic random access memory (DRAM). The system 500 may also include a graphics coprocessor 513, however incorporation of the graphics coprocessor 513 into the system 500 is not necessary to the operation of the system 500. Coupled to the I/O bus 508 may be a display device 514, a mass storage device 520, and keyboard and pointing devices 522.
These elements perform their conventional functions well known in the art. In particular, mass storage 520 may be used to provide long-term storage for the executable instructions for a method for forming microelectronic structures in accordance with embodiments of the present invention, whereas main memory 512 may be used to store on a shorter term basis the executable instructions of a method for forming microelectronic structures in accordance with embodiments of the present invention during execution by computing device 502. In addition, the instructions may be stored on other machine readable mediums accessible by the system, such as compact disk read only memories (CD-ROMs), digital versatile disks (DVDs), and floppy disks, for example. In one embodiment, main memory 512 may supply the computing device 502 (which may be a processor, for example) with the executable instructions for execution.
Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that various microelectronic structures, such as transistor structures, are well known in the art. Therefore, the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
