Micro power micro-sized CMOS active pixel

Information

  • Patent Grant
  • 6388242
  • Patent Number
    6,388,242
  • Date Filed
    Thursday, October 14, 1999
    25 years ago
  • Date Issued
    Tuesday, May 14, 2002
    22 years ago
Abstract
Reduced size CMOS active pixel circuit uses special transistors with their gates and sources connected together. This transistor is placed at the top of the pixel.
Description




BACKGROUND




Active pixel sensors are well known in the art. A basic active pixel sensor is described in U.S. Pat. No. 5,471,515. An active pixel sensor typically includes a plurality of pixel circuitry units. Each unit, or “pixel” includes a photoreceptor, a buffer, and a select transistor. Some means of resetting the pixel is also provided.




It is desirable to make each pixel as small as possible to enable more pixels to fit on a single chip. For example, a desirable size in current technology is 5×5 μm


2


. It is also desirable to keep the supply voltages low as possible. For example, it would be useful if an active pixel sensor could operate from a single 1.5 volt battery. This provides limitations on the way in which such a device can operate.




SUMMARY




The present application features a new pixel structure which has certain advantages, and can operate using relatively low power.




The present application defines an active pixel unit, that has a charge accumulating part, having a capability of accumulating charge therein; a photoreceptor, connected to said charge accumulating part, and changing an amount of charge therein based on an applied received charge; a reset transistor, having its drain and gate connected together, and connected to reset said charge accumulating part; and a select transistor, also having its drain and gate connected together, and connected to select an output of said charge accumulating part.











BRIEF DESCRIPTION OF THE DRAWINGS




These and other aspects of the invention will be described in detail with reference to the accompanying drawings, wherein:





FIG. 1

shows a schematic diagram of the exemplary pixel; and





FIG. 2

shows a layout of the exemplary pixel.











DESCRIPTION OF THE EMBODIMENTS




The pixel schematic is shown in FIG.


1


. The pixel includes three transistors M


1


, M


2


and M


3


which are configured and connected together in a new way.




A floating diffusion


115


collects charge. This can include an integration capacitor


110


, which can be formed from a dedicated capacitor, or from stray capacitance.




The reset transistor M


2


controls the passage of reset level


100


to the integration capacitor


110


. Integration capacitor


110


is reset to the high level of the reset signal. A desirable value is about 1.6 volts.




The reset transistor M


2


has a drain


102


and gate


104


which are connected together. This allows charging the floating diffusion


115


to a potential that is higher than VDD. The reset pulse


100


, for example, can be produced by a booster, e.g. a charge pump. By using this system, the floating diffusion


115


, with the integration capacitor


110


connected thereto, can be charged to a higher level, even if low voltage operation is used.




The reset level of the capacitor is sampled as described herein.




After reset, the photodiode


120


receives photons indicative of light applied to that particular pixel. The charging of the photodiode discharges the integration capacitor


110


. The amount of discharge of the integration capacitor


110


eventually sets the amount of received charge on the pixel.




At the end of the integration period, the select line


130


is brought active. This turns on the transistor M


1


, whose drain and gate are also connected together. The select value is passed through the transistor M


1


to the drain of M


3


, configured as a source follower transistor. The source


142


of M


3


produces an output indicative of the reset value on the capacitor


110


, minus the amount of charge discharged, through the photodiode


120


.




While the select value is still on, the integration capacitor is reset as described above. The reset value is also read from the output in preparation for the next integration cycle. In addition, the select transistor M


1


can be placed physically on top of the active pixel source follower transistor. This allows a new layout consideration which was not previously enabled by the art. This can also improve the gain and dynamic range of the source follower.




Other embodiments are within the disclosure.



Claims
  • 1. An active pixel unit, comprising:a charge accumulating part, having a capability of accumulating charge therein; a photoreceptor, connected to said charge accumulating part, and changing an amount of charge therein based on an applied received charge; a reset transistor, having its drain and gate connected together, and connected to reset said charge accumulating part; and a select transistor, also having its drain and gate connected together, and connected to select an output of said charge accumulating part.
  • 2. A device as in claim 1 wherein said select transistor is physically at the top of said pixel.
  • 3. A device as in claim 1 wherein said photoreceptor includes a photodiode.
  • 4. A unit as in claim 1, further comprising a source follower circuit, connected to said select transistor.
CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the U.S. Provisional Application No. 60/104,295, filed on Oct. 14, 1998.

US Referenced Citations (4)
Number Name Date Kind
5471515 Fossum et al. Nov 1995 A
5880460 Merrill Mar 1999 A
6097022 Merrill et al. Aug 2000 A
6140630 Rhodes Oct 2000 A
Provisional Applications (1)
Number Date Country
60/104295 Oct 1998 US