Claims
- 1. A method of fabricating a microbellows actuator membrane, comprising:
- obtaining a support substrate;
- growing a support substrate protectant layer on said support substrate;
- first depositing a first sacrificial layer on top of said support substrate protectant layer;
- second depositing a first structural layer on top of said first sacrificial layer;
- third depositing a second sacrificial layer on top of said first structural layer;
- patterning said second sacrificial layer to open a contact window between said first structural layer and a second structural layer;
- fourth depositing said second structural layer on top of said second sacrificial layer;
- patterning said second structural layer;
- fifth depositing a third sacrificial layer on top of said second structural layer;
- patterning said third sacrificial layer;
- sixth depositing a third structural layer on top of said third sacrificial layer;
- patterning said third structural layer;
- etching a back side of said support substrate and a portion of said support substrate protectant layer forming an opening;
- immersing said support substrate with said first, second, third sacrificial layers and said first, second, third structural layers in an etchant;
- removing said first, second, third sacrificial layer thereby releasing the microbellows actuator membrane.
- 2. A method as in claim 1, wherein said support substrate is made of silicon.
- 3. A method as in claim 1, wherein said support substrate protectant is made of thermal oxide.
- 4. A method as in claim 1, wherein said support substrate protectant layer is 0.5 .mu.m thick.
- 5. A method as in claim 1, wherein said first sacrificial layer is LPCVD undoped polysilicon.
- 6. A method as in claim 1, wherein said first depositing is done at above 600 degrees Celsius.
- 7. A method as in claim 1, wherein said second sacrificial layer is LPCVD undoped polysilicon.
- 8. A method as in claim 1, wherein said third depositing is done at above 600 degrees Celsius.
- 9. A method as in claim 1, wherein said third sacrificial layer is LPCVD undoped polysilicon.
- 10. A method as in claim 1, wherein said fifth depositing is done at above 600 degrees Celsius.
- 11. A method as in claim 1, wherein said first structural layer is LPCVD silicon nitride.
- 12. A method as in claim 1, wherein said second depositing is done at approximately 835 degrees Celsius.
- 13. A method as in claim 1, wherein said second depositing is at a 4:1 dichlorosilane (DCS):NH.sub.3 flow ratio.
- 14. A method as in claim 1, wherein said second structural layer is LPCVD silicon nitride.
- 15. A method as in claim 1, wherein said fourth depositing is done at approximately 835 degrees Celsius.
- 16. A method as in claim 1, wherein said fourth depositing is at a 4:1 dichlorosilane (DCS):NH.sub.3 flow ratio.
- 17. A method as in claim 1, wherein said third structural layer is LPCVD silicon nitride.
- 18. A method as in claim 1, wherein said sixth depositing is done at approximately 835 degrees Celsius.
- 19. A method as in claim 1, wherein said sixth depositing is at a 4:1 dichlorosilane (DCS):NH.sub.3 flow ratio.
- 20. A method as in claim 1, wherein said etching is done with KOH.
- 21. A method as in claim 1, wherein said immersing is done in TMAH solution.
- 22. A method as in claim 1, wherein said immersing is done at around 90 degrees Celsius.
- 23. A method as in claim 1, further comprising forming anchor structures at points where one structural layer contacts another structural layer.
- 24. A method as in claim 23, wherein said anchor structures are strengthened by forming an additional block portion adjacent to said anchor structures.
- 25. A method as in claim 24, wherein said additional block portion is made of polysilicon.
- 26. A method as in claim 24, wherein said additional block portion is made of polysilicon doped with boron.
- 27. A method as in claim 24, wherein said additional block portion is a polysilicon block containing 4.times.10.sup.2 boron atoms/cm.sup.3.
- 28. A method as in claim 1, wherein said first structural layer is made of Parylene.
- 29. A method as in claim 1, wherein said second structural layer is made of Parylene.
- 30. A method as in claim 1, wherein said third structural layer is made of Parylene.
- 31. A method as in claim 1, further comprising forming additional structural layers on top of said third structural layer.
- 32. A method as in claim 1, wherein said additional structural layers are made of Parylene.
- 33. A method as in claim 1, wherein said additional structural layers are made of silicon nitride.
- 34. A method as in claim 1, wherein said first, second, third structural layers are deposited at a certain dichlorosilane:NH.sub.3 ratio sufficient to reduce tensile stress and minimize cracking of said structural layers.
- 35. A method as in claim 1, wherein said additional structural layers are deposited at a certain dichlorosilane:NH.sub.3 ratio sufficient to reduce tensile stress and minimize cracking of said structural layers.
Parent Case Info
This is a divisional of U.S. application Ser. No. 09/057,381, filed Apr. 8, 1998, now U.S. Pat. No. 6,069,392, and claims benefit to U.S. Provisional application Ser. No. 60/077,945, filed Mar. 13, 1998, and U.S. Provisional application Ser. No. 60/043,463, filed Apr. 11, 1997.
Government Interests
U.S. Government may have certain rights in this invention pursuant to Grant No. N66001-96-C-8632 awarded by the U.S. Navy.
US Referenced Citations (12)
Foreign Referenced Citations (1)
| Number |
Date |
Country |
| 5-90616 |
Apr 1993 |
JPX |
Non-Patent Literature Citations (1)
| Entry |
| Barron, C.C. et al "Sample (Sandia Agile MEMS Prototyping, Layout tools, and Education)" Proceedings of SPIE, Micromachining and Microfabrication Process Technology III, vol. 3223, pp. 10-15, Sep. 1997. |
Divisions (1)
|
Number |
Date |
Country |
| Parent |
057381 |
Apr 1998 |
|