Patent Application
20230140814
An embodiment of the present invention relates generally to microelectronic buildup redistribution layer system.
Electromagnetic interference (EMI) is prevalent throughout the conductor circuits in the test interface substate. As semiconductor fabrication technology advances continue to be implemented, the critical dimension or spacing between electrical test contact pads and bumps pitch of dies or chips on the semiconductor wafer continues to shrink. Apparently, testing probe head comprising a plurality of testing probe are also increasing in numbers with pitch between probes getting smaller for wafer level testing and devices.
A technology bottleneck occurs that is associated with existing known testing probe head designs and probe assembly techniques that do not readily support such EMI protection in small testing pad micro bump pitches in wafer level testing and devices.
The shielding and dielectric insulation around the probe head probe area can reduces electrical noise and reduces its impact on signals and also lowers electromagnetic radiation for the better and reliable testing. Shielding also prevents crosstalk between near or surrounding probes and test pads.
As users become more empowered with the growth of computing devices, new and old paradigms begin to take advantage of this new device space. There are many technological solutions to take advantage of this new device capability and device miniaturization. However, reliable testing and faster delivery of wafers through new devices has become a concern for manufactures.
Thus, a need still remains for a microelectronic buildup redistribution layer system for testing of wafers and devices. In view of the ever-increasing high-speed applications and performance, better commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Additionally, the need to provide manufacturing capabilities of redistribution system to provide the EMI vertical shield on the test substrate top (wafer or device) side to provide the shields on the contact points of probe head probes. This improves efficiencies, performance and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
An embodiment of the present invention provides a microelectronic buildup redistribution layer system, including: a base carrier substrate; conductor traces and a dielectric structure on the substrate, including a plurality of multi-layers.
An embodiment of the present invention provides a method of manufacture thereof providing vertical EMI vertical shield and/or dielectric insulation on the test substrate top (wafer or device) side to provide the shields on the contact points of probe head probes. Microelectronic buildup redistribution layer system including: providing a base carrier substrate; forming a plurality of multi-layers on the substrate, conductor traces, conductor vias and a dielectric structure on the substrate.
Certain embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. The steps or elements will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of an embodiment of the present invention.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring an embodiment of the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
The drawings showing embodiments of the system are semi-diagrammatic, and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing figures. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the figures is arbitrary for the most part. Generally, the invention can be operated in any orientation.
In this embodiment, the buildup redistribution vertical electrical shield on top layer probe head contact pads. Shields are connected to the single ground layer. However, it can be routed and connected with any layers and conductors.
The designation and usage of the term first, second, third, etc. is for convenience and clarity and is not meant limit a particular order. The steps or processes described can be performed in any order to implement the claimed subject matter.
Referring now to
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The redistribution platform 700 is a structure for providing interconnection between two devices. For example, the redistribution platform 700 can be a space transformer, a redistribution structure for a multi-die package, or a combination thereof. The redistribution platform 700 can provide electrical and functional connectivity between semiconductor wafer 630, the die 640, or a combination thereof, and the rest of the redistribution system 800.
Referring now to
The base carrier substrate 500 can be a rigid foundation or base layer for the redistribution player platform 300. The substrate 500 can include an electrically insulating material, such as a ceramic based or polymer composite based material.
For illustrate purpose, the probe head system 620 is shown and align to buildup redistribution top layer system 105 test pad 110.
The microelectronics buildup redistribution system 300 layers can be signal layer, ground layer, power and plane layer or the combination thereof.
Referring now to
The redistribution platform 300 and probe head system 620 can provide electrical and functional connectivity between the semiconductor wafer, semiconductor dice, or a combination thereof for system testing, such as wafer testing, die testing, package testing, or inter-package testing.
Referring now to
The buildup redistribution top layer test pad 110 is normally plated with Nickle (Ni) and Hard Gold (Au), but not limited to these earth metal.
The platform system 650 is showing the gap (open area) between the test pad and the buildup redistribution vertical shield is filled with the dielectric insulator 250, such as solder mask, polyimide, epoxy, or other polymer materials. For example, this can prevent the probe pin 630 slid in the gap which can cause the pin damage.
Referring now to
It has been discovered that the offset of X and Y coordinates probe pin and the test pad can damage the pads and test pads. The inner vertical shield wall can also provide the protection.
For illustration purpose, the buildup redistribution top layer test pad system 110 depicted the one shape, although it is understood that the system 110 can have a different shape, thickness (height) and type. For example, the redistribution top layer test pad system 110 can have the multiple of thousands test pads, and the pad-to-pad distance (pitch) can in range micron (μm).
Based on the buildup redistribution test pad shape and sizes, the buildup redistribution buildup shield and insulators can also have a different shape, thickness (height) and type.
Referring now to
The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization. Another important aspect of an embodiment of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
These and other valuable aspects of an embodiment of the present invention consequently further the state of the technology to at least the next level.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of a foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
