Claims
- 1. In a multiprocessor architecture capable of supporting a plurality of microprocessors, each of said microprocessors having a data (D) cache, an instruction (I) cache, a memory port, and an input/output unit (IOU), a memory control unit (MCU) in each of said microprocessors comprising:
a switch network; a D-cache interface circuit; means for coupling said D-cache interface circuit between said D-cache and said switch network; an I-cache interface circuit; means for coupling said I-cache interface circuit between said I-cache and said switch network; an I/O interface circuit; means for coupling said I/O interface circuit between said IOU and said switch network; a memory port interface circuit; means for coupling said memory port interface circuit between said memory port and said switch network; switch arbitration means for arbitrating for said switch network; port arbitration means for arbitrating for said memory port; means for transferring to said port arbitration means a request to transfer data between one of said D-cache, said I-cache and said IOU and said memory port through said switch network and said port interface circuit; means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said D-cache, said I-cache and IOU and said memory port.
- 2. An MCU according to claim 1 wherein said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD) and further comprising:
means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including a MAU address bus, an MAU data bus and an MAU control signal bus; means for temporarily storing an address associated with a request to write to said MAU from one of said D cache and said IOU if said MAU address bus is not then available to receive-said address; means for temporarily storing write data from said source of said request to write to said MAU if said MAU data bus is not then available to receive said write data; means for transferring said address associated with said request to write to said MAU from said source of said request to write to said MAU to said switch request bus (SW_REQ) and said write data associated therewith to said switch write data bus (SW_WD); means for transferring said address associated with said request to write to said MAU from said switch request bus (SW_REQ) to said means for temporarily storing said address associated with said request to write to said MAU; means for transferring said write data from said switch write data bus (SW_WD) to said means for temporarily storing said write data; and means for transferring said address from said means for temporarily storing said address to said MAU address bus and said write data from said means for temporarily storing said write data to said MAU address and write data buses when said MAU address and write data buses are available to receive said address-and said write data.
- 3. An MCU according to claim 1 wherein said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD) and further comprising:
means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means for temporarily storing an address associated with a read request to read data from said MAU from one of said D-cache, I-cache and IOU if said MAU address bus is not then available to receive said address; means for temporarily storing said read data from said MAU if said switch read data bus (SW_RD) is not then available to transfer said read data; means for transferring said address associated with said read request from said source of said request to said switch request bus (SW_REQ) when said switch request bus (SW_REQ) is available; means for transferring said address associated with said read request from said switch request bus (SW_REQ) to said means for temporarily storing said address associated with said read request if said MAU address bus is not then available to receive said address; means for transferring said read data from said MAU data bus to said means for temporarily storing said read data when said MAU address bus is available to receive said address and said switch read bus (SW_RD) is not available to transfer said read data; and means for transferring said read data from said means for temporarily storing said read data to said switch read data bus (SW_RD) and from said switch read data bus (SW_RD) to said source of said request when said switch read data bus (SW_RD) is available to transfer said read data.
- 4. An MCU according to claim 1 wherein said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD) and further comprising:
means for transferring a request for an I/O data transfer between one of said D-cache and said I-cache and said IOU through said switch network and said I/O interface circuit; means for sending an IOU available signal from said I/O interface circuit to said switch arbitration means when said I/O interface circuit is available to process said request for an I/O data transfer; and means for transferring an address associated with said request for an I/O data transfer to said I/O interface circuit via said switch request bus (SW_REQ) when said switch network is available to process said request.
- 5. An MCU according to claim 1 wherein said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD) and further comprising:
means for transferring write data from one of said D-cache and I-cache to said I/O interface circuit via said switch write data bus (SW_WD) when said request for an I/O data transfer is a write request; and means for transferring read data from said IOU circuit to one of said D-cache and I-cache via said switch read data bus (SW_RD) when said request for an I/O data transfer is a read request.
- 6. An MCU according to claim 1 comprising:
means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; a test and set bypass circuit, said test and set bypass circuit having a snoop address generator coupled to said MAU address bus for generating snoop addresses corresponding to addresses on said MAU address bus and a content addressable memory (CAM); means responsive to the execution of a predetermined instruction associated with a request to access a shared memory region for storing the address of a semaphore associated with said region in said CAM; means for comparing said snoop addresses with the contents of said CAM on subsequent requests for said semaphore; and means for sending a semaphore failed signal to the source of said request for said semaphore if said semaphore address is still resident in said CAM to thereby save memory bandwidth.
- 7. An MCU according to claim 6 comprising:
means responsive to a write to said shared memory region for releasing said semaphore and clearing said CAM.
- 8. A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:
means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read request from said master; means for providing an intervention signal (ITV) to said master when one of said slaves has modified the data associated with said address placed on said MAU address bus by said master; means responsive to said ITV signal for causing said master to disregard the data received from said address associated with said read request; and means for writing said modified data in said slave to said address associated with said read request.
- 9. A multiprocessor architecture according to claim 8 further comprising:
a memory port; a port interface circuit for controlling transfers of data through said port; means for holding said read request from said master in said port interface circuit while said slave writes said modified data to memory; and means for thereafter executing said read request from said master.
- 10. A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:
means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a write request from said master; and means for causing each of said slaves having data in a cache from said address associated with said write request to invalidate said data in said cache.
- 11. A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:
means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master; means for providing an intervention signal (ITV) to said master when one of said slaves has modified the data from said address associated with said read-with-intent-to-modify request from said master; means responsive to said ITV signal for causing said master to disregard the data received from said address associated with said read-with-intent-to-modify request; and means for writing said modified data in said slave to said address associated with said read-with-intent-to-modify request.
- 12. A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:
means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master; and means for causing each of said slaves having unmodified data from said address associated with said write request to invalidate said data.
- 13. A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:
means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means for comparing successive addresses appearing on the MAU address bus; and means responsive to said comparing means for continuously asserting a row address strobe (RAS) so long as said successive addresses appearing on said MAU address bus comprise the same row address.
- 14. A multiprocessor architecture capable of supporting multiple processors according to claim 1 comprising:
means for providing a dynamic priority to IOU, D-cache and I-cache device requests as a function of intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption, said dynamic priority providing means including counting means for keeping track of the number of times each of said factors occurs and means responsive to said counting means for changing the priority of said devices as a function of said intrinsic priority and said number.
- 15. A multiprocessor architecture capable of supporting multiple processors comprising:
means located in each of said processors for generating a memory refresh request after a predetermined number of machine cycles; means located in each of said processors for keeping track of the number of times said request is denied since the last time it was granted; and means located in each of said processors for increasing the priority of said memory refresh request when said number reaches a predetermined magnitude, such that said memory is refreshed within a predetermined time period.
- 16. A method of transferring data in a multiprocessor architecture capable of supporting a plurality of microprocessors, each of said microprocessors having a data (D) cache, an instruction (I) cache, a memory port, an input/output unit (IOU) and a memory control unit (MCU), said MCU having a switch network, a D-cache interface circuit, means for coupling said D-cache interface circuit between said D-cache and said switch network, an I-cache interface circuit, means for coupling said I-cache interface circuit between said I-cache and said switch network, an I/O interface circuit, means for coupling said I/O interface circuit between said IOU and said switch network, a memory port interface circuit, means for coupling said memory port interface circuit between said memory port and said switch network, switch arbitration means for arbitrating for said switch network and port arbitration means for arbitrating for said memory port, comprising the steps of:
transferring to said port arbitration means a request to transfer data between one of said D-cache, said I-cache and said IOU and said memory port through said switch network and said port interface circuit; transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said D-cache, said I-cache and IOU and said memory port.
- 17. A method of transferring data in a multiprocessor according to claim 16 wherein said architecture comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD), further comprising the steps of:
temporarily storing an address associated with a request to write to said MAU from one of said D cache and said IOU if said MAU address bus is not then available to receive said address; temporarily storing write data from said source of said request to write to said MAU if said MAU data bus is not then available to receive said write data; transferring said address associated with said request to write to said MAU from said source of said request to write to said MAU to said switch request bus (SW_REQ) and said write data associated therewith to said switch write data bus (SW_RD); transferring said address associated with said request to write to said MAU from said switch request bus (SW_REQ) to said means for temporarily storing said address associated with said request to write to said MAU; transferring said write data from said switch write data bus (SW_WD) to said means for temporarily storing said write data; and transferring said address from said means for temporarily storing said address to said MAU address bus and said write data from said means for temporarily storing said write data to said MAU address and write data buses when said MAU address and write data buses are available to receive said address and said write data.
- 18. A method of transferring data in a multiprocessor according to claim 16 wherein said architecture comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and said switch network comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD), further comprising the steps of:
temporarily storing an address associated with a read request to read data from said MAU from one of said D-cache, I-cache and IOU if said MAU address bus is not then available to receive said address; temporarily storing said read data from said MAU if said switch read data bus (SW_RD) is not then available to transfer said read data; transferring said address associated with said read request from said source of said request to said switch request bus (SW_REQ) when said switch request bus (SW_REQ) is available; transferring said address associated with said read request from said switch request bus (SW_REQ) to said means for temporarily storing said address associated with said read request if said MAU address bus is not then available to receive said address; transferring said read data from said MAU data bus to said means for temporarily storing said read data when said MAU address bus is available to receive said address and said switch read bus (SW_RD) is not available to transfer said read data; and transferring said read data from said means for temporarily storing said read data to said switch read data bus (SW_RD) and from said switch read data bus (SW_RD) to said source of said request when said switch read data bus (SW_RD) is available to transfer said read data.
- 19. A method of transferring data in a multiprocessor architecture according to claim 16 wherein said switch network in said architecture comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD), further comprising the steps of:
transferring a request for an I/O data transfer between one of said D-cache and said I-cache and said IOU through said switch network and said I/O interface circuit; sending an IOU available signal from said I/O interface circuit to said switch arbitration means when said I/O interface circuit is available to process said request for an I/O data transfer; and transferring an address associated with said request for an I/O data transfer to said I/O interface circuit via said switch request bus (SW_REQ) when said switch network is available to process said request.
- 20. A method of transferring data in a multiprocessor architecture according to claim 16 wherein said switch network in said architecture comprises a switch request bus (SW_REQ), a switch write data bus (SW_WD), and a switch read data bus (SW_RD), further comprising the steps of:
transferring write data from one of said D-cache and I-cache to said I/O interface circuit via said switch write data bus (SW_WD) when said request for an I/O data transfer is a write request; and transferring read data from said IOU circuit to one of said D-cache and I-cache via said switch read data bus (SW_RD) when said request for an I/O data transfer is a read request.
- 21. A method of transferring data in a multiprocessor architecture according to claim 16 wherein said architecture comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and a test and set bypass circuit, said test and set bypass circuit having a snoop address generator coupled to said MAU address bus for generating snoop addresses corresponding to addresses on said MAU address bus and a content addressable memory (CAM) comprising the steps of:
storing the address of a semaphore associated with a shared memory region in said CAM; comparing said snoop addresses with the contents of said CAM on subsequent requests for said semaphore; and sending a semaphore failed signal to the source of said request for said semaphore if said semaphore address is still resident in said CAM to thereby save memory bandwidth.
- 22. A method according to claim 21 comprising the steps of:
releasing said semaphore and clearing said CAM in response to a write to said shared memory region.
- 23. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:
enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read request from said master; providing an intervention signal (ITV) to said master when one of said slaves has modified the data associated with said address placed on said MAU address bus by said master; causing said master to disregard the data received from said address associated with said read request in response to said ITV signal; and writing said modified data in said slave to said address associated with said read request.
- 24. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:
enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a write request from said master; and causing each of said slaves having data in a cache from said address associated with said write request to invalidate said data in said cache.
- 25. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:
enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master; providing an intervention signal (ITV) to said master when one of said slaves has modified the data from said address associated with said read-with-intent-to-modify request from said master; causing said master to disregard the data received from said address associated with said read-with-intent-to-modify request in response to said ITV signal; and writing said modified data in said slave to said address associated with said read-with-intent-to-modify request.
- 26. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:
enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master; and causing each of said slaves having unmodified data from said address associated with said write request to invalidate said data.
- 27. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:
comparing successive addresses appearing on the MAU address bus; and continuously asserting a row address strobe (RAS) so long as said successive addresses appearing on said MAU address bus comprise the same row address.
- 28. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors comprising the steps of:
providing a dynamic priority to IOU, D-cache and I-cache device requests as a function of intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption; keeping track of the number of times each of said factors occurs; and changing the priority of said devices as a function of said intrinsic priority and said number.
- 29. A method of dynamically refreshing a memory in a multiprocessor architecture capable of supporting multiple processors comprising the steps of:
generating a memory refresh request after a predetermined number of machine cycles in each of said processors; keeping track of the number of times said request is denied since the last time it was granted; and increasing the priority of said memory refresh request when said number reaches a predetermined magnitude such that said memory is refreshed within a predetermined time period by at least one of said processors.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is related to the following applications, all assigned to the Assignee of the present application:
[0002] 1. HIGH-PERFORMANCE RISC MICROPROCESSOR ARCHITECTURE, invented by Le Nguyen et al, SMOS-7984MCF/GBR, application Ser. No. ______, filed ______;
[0003] 2. EXTENSIBLE RISC MICROPROCESSOR ARCHITECTURE, invented by Quang Trang et al, SMOS-7985MCF/GBR, application Ser. No. ______, filed ______;
[0004] 3. RISC MICROPROCESSOR ARCHITECTURE WITH ISOLATED ARCHITECTURAL DEPENDENCIES, invented by Yoshi Miyayama, SMOS-7987MCF/GBR/RCC, application Ser. No. ______, filed ______;
[0005] 4. RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS, invented by Sanjiv Garg, SMOS-7988MCF/GBR/RCC, application Ser. No. ______, filed ______;
[0006] 5. RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE, invented by Quang Trang et al, SMOS-7989MCF/GBR/WSW, application Ser. No. ______, filed ______;
[0007] 6. SINGLE CHIP PAGE PRINTER CONTROLLER, invented by Derek J. Lentz, SMOS-7991MCF/GBR/HKW, application Ser. No. ______, filed ______.
Divisions (2)
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Number |
Date |
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Parent |
08915913 |
Aug 1997 |
US |
Child |
09253761 |
Feb 1999 |
US |
Parent |
07726893 |
Jul 1991 |
US |
Child |
08442649 |
May 1995 |
US |
Continuations (3)
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09884943 |
Jun 2001 |
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Child |
10449018 |
Jun 2003 |
US |
Parent |
09253761 |
Feb 1999 |
US |
Child |
09884943 |
Jun 2001 |
US |
Parent |
08442649 |
May 1995 |
US |
Child |
08915913 |
Aug 1997 |
US |