Patent Application
20050188182
(C) Copyright 2000 Texas Instruments Incorporated. A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation, and particularly relates to microprocessors optimized for digital signal processing.
Generally, a microprocessor is a circuit that combines the instruction-handling, arithmetic, and logical operations of a computer on a single semiconductor integrated circuit. Microprocessors can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microprocessors. General-purpose microprocessors are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit (CPU) in equipment such as personal computers. Special-purpose microprocessors, in contrast, are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microprocessor. By knowing the primary function of the microprocessor, the designer can structure the microprocessor architecture in such a manner that the performance of the specific function by the special-purpose microprocessor greatly exceeds the performance of the same function by a general-purpose microprocessor regardless of the program implemented by the user.
One such function that can be performed by a special-purpose microprocessor at a greatly improved rate is digital signal processing. Digital signal processing generally involves the representation, transmission, and manipulation of signals, using numerical techniques and a type of special-purpose microprocessor known as a digital signal processor (DSP). Digital signal processing typically requires the manipulation of large volumes of data, and a digital signal processor is optimized to efficiently perform the intensive computation and memory access operations associated with this data manipulation. For example, computations for performing Fast Fourier Transforms (FFTs) and for implementing digital filters consist to a large degree of repetitive operations such as multiply-and-add and multiple-bit-shift. DSPs can be specifically adapted for these repetitive functions, and provide a substantial performance improvement over general-purpose microprocessors in, for example, real-time applications such as image and speech processing.
DSPs are central to the operation of many of today's electronic products, such as high-speed modems, high-density disk drives, digital cellular phones, complex automotive systems, and video-conferencing equipment. DSPs will enable a wide variety of other digital systems in the future, such as video-phones, network processing, natural speech interfaces, and ultra-high speed modems. The demands placed upon DSPs in these and other applications continue to grow as consumers seek increased performance from their digital products, and as the convergence of the communications, computer and consumer industries creates completely new digital products.
Microprocessor designers have increasingly endeavored to exploit parallelism to improve performance. One parallel architecture that has found application in some modern microprocessors utilizes multiple instruction fetch packets and multiple instruction execution packets with multiple functional units.
Digital systems designed on a single integrated circuit are referred to as an application specific integrated circuit (ASIC). MegaModules are being used in the design of ASICs to create complex digital systems a single chip. (MegaModule is a trademark of Texas Instruments Incorporated.) Types of MegaModules include SRAMs, FIFOs, register files, RAMs, ROMs, universal asynchronous receiver-transmitters (UARTs), programmable logic arrays and other such logic circuits. MegaModules are usually defined as integrated circuit modules of at least 500 gates in complexity and having a complex ASIC macro function. These MegaModules are predesigned and stored in an ASIC design library. The MegaModules can then be selected by a designer and placed within a certain area on a new IC chip.
Designers have succeeded in increasing the performance of DSPs, and microprocessors in general, by increasing clock speeds, by removing data processing bottlenecks in circuit architecture, by incorporating multiple execution units on a single processor circuit, and by developing optimizing compilers that schedule operations to be executed by the processor in an efficient manner. The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture.
An illustrative embodiment of the present invention seeks to provide a microprocessor, and a method for operating a microprocessor that improves digital signal processing performance. Aspects of the invention are specified in the claims.
In an embodiment of the present invention, a digital signal processor is provided with byte intermingling circuitry for selecting fields from a selected pair of source operands and intermingling the selected fields in an order in accordance with each one of a set of byte intermingling instructions.
In an embodiment of the invention, a 32-bit operand is treated as four 8-bit byte fields and the four fields are selected separately. In another embodiment, an operand size different from 32-bits may be operated on, and the field sizes may be different than eight bits.
In an embodiment of the invention, one instruction is provided that performs a shift right and byte merge operation. Another instruction is provided that performs a shift left and byte merge operation. Another instruction is provided that perform a byte swap operation. A set of instructions are provided that perform various byte packing and unpacking operations.
Other features and advantages of the present invention will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:
In microprocessor 1 there are shown a central processing unit (CPU) 10, data memory 22, program memory 23, peripherals 60, and an external memory interface (EMIF) with a direct memory access (DMA) 61, coupled to data memory 22 via lines 43. CPU 10 further has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit (“ALU”) L1, a shared multiport register file 20a from which data are read and to which data are written. Instructions are fetched by fetch unit 10a from instruction memory 23 over a set of busses 41. Decoded instructions are provided from the instruction fetch/decode unit 10a-c to the functional units D1, M1, S1, and L1 over various sets of control lines which are not shown. Data are provided to/from the register file 20a from/to to load/store units D1 over a first set of busses 32a, to multiplier M1 over a second set of busses 34a, to ALU/shifter unit S1 over a third set of busses 36a and to ALU L1 over a fourth set of busses 38a. Data are provided to/from the memory 22 from/to the load/store units D1 via a fifth set of busses 40a. Note that the entire data path described above is duplicated with register file 20b and execution units D2, M2, S2, and L2. In this embodiment of the present invention, two unrelated aligned double word (64 bits) load/store transfers can be made in parallel between CPU 10 and data memory 22 on each clock cycle using bus set 40a and bus set 40b.
A single non-aligned double word load/store transfer is performed by scheduling a first .D unit resource and two load/store ports on memory 22. Advantageously, an extraction circuit is connected to the memory subsystem to provide a non-aligned data item extracted from two aligned data items requested by the .D unit. Advantageously, a second .D unit can perform 32-bit logical or arithmetic instructions in addition to the .S and .L units while the address port of the second .D unit is being used to transmit one of two contiguous addresses provided by the first .D unit. Furthermore, a non-aligned access near the end of a circular buffer region in the target memory provides a non-aligned data item that wraps around to the other end of the circular buffer.
Emulation circuitry 50 provides access to the internal operation of integrated circuit 1 that can be controlled by an external test/development system (XDS) 51. External test system 51 is representative of a variety of known test systems for debugging and emulating integrated circuits. One such system is described in U.S. Pat. No. 5,535,331 which is incorporated herein by reference. Test circuitry 52 contains control registers and parallel signature analysis circuitry for testing integrated circuit 1.
Note that the memory 22 and memory 23 are shown in
When microprocessor 1 is incorporated in a data processing system, additional memory or peripherals may be connected to microprocessor 1, as illustrated in
In the present embodiment, CPU core 10 is encapsulated as a MegaModule, however, other embodiments of the present invention may be in custom designed CPU's or mass market microprocessors, for example.
A detailed description of various architectural features of the microprocessor of
The general-purpose register files support data ranging in size from packed 8-bit data through 64-bit fixed-point data. Values larger than 32 bits, such as 40-bit long and 64-bit double word quantities, are stored in register pairs, with the 32 LSBs of data placed in an even-numbered register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). Packed data types store either four 8-bit values or two 16-bit values in a single 32-bit register.
There are 32 valid register pairs for 40-bit and 64-bit data, as shown in Table 1. In assembly language syntax, a colon between the register names denotes the register pairs and the odd numbered register is encoded in the instruction opcode.
For 40-bit data, operations requiring a long input ignore the 24 MSBs of the odd register. Operations producing a long result zero-fill the 24 MSBs of the odd register. The even register is encoded in the opcode.
The eight functional units in processor 10's data paths are be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. The functional units are described in Table 2.
Besides being able to perform 32-bit data manipulations, processor 10 also contains many 8-bit and 16-bit data instructions in the instruction set. For example, the MPYU4 instruction performs four 8×8 unsigned multiplies with a single instruction on a .M unit. The ADD4 instruction performs four 8-bit additions with a single instruction on a .L unit.
Most data lines in the CPU support 32-bit operands, and some support long (40-bit) and double word (64-bit) operands. Each functional unit has its own 32-bit write port into a general-purpose register file (Refer to
Register File Cross Paths
Each functional unit reads directly from and writes directly to the register file within its own data path. That is, .L1 unit 18a, .S1 unit 16a, .D1 unit 12a, and .M1 unit 14a write to register file A and .L2 unit 18b, .S2 unit 16b, .D2 unit 12b, and .M2 unit 14b write to register file B. The register files are connected to the opposite-side register file's functional units via the 1X and 2X cross paths. These cross paths allow functional units from one data path to access a 32-bit operand from the opposite side's register file. The 1X cross path 210 allows data path A's functional units to read their source from register file B, via multiplexers 211, 212, 213, 214. Similarly, the 2X cross path allows data path B's functional units to read their source from register file A.
All eight of the functional units have access to the opposite side's register file via a cross path. The .M1, .M2, .S1, .S2, .D1, and .D2 units' src2 inputs are selectable between the cross path and the same side register file. In the case of the .L1 and .L2 units 18a, 18b, both src1 and src2 inputs are also selectable between the cross path and the same-side register file, for example by operation of multiplexers 211, 212 as shown in
Only two cross paths, 1X and 2X, exist in this embodiment of the architecture. Thus the limit is one source read from each data path's opposite register file per cycle, or a total of two cross-path source reads per cycle. Advantageously, multiple units on a side may read the same cross-path source simultaneously. Thus the cross path operand for one side may be used by any one, multiple or all the functional units on that side in an execute packet. In the C62x/C67x, only one functional unit per data path, per execute packet could get an operand from the opposite register file.
A delay clock cycle is introduced whenever an instruction attempts to read a register via a cross path that was updated in the previous cycle. This is known as a cross path stall. This stall is inserted automatically by the hardware, as suggested by delay block 250 in
Memory, Load and Store Paths
Processor 10 supports double word loads and stores. There are four 32-bit paths for loading data for memory to the register file. For side A, LD1a is the load path for the 32 LSBs; LD1b is the load path for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs; LD2b is the load path for the 32 MSBs. There are also four 32-bit paths, for storing register values to memory from each register file. ST1a is the write path for the 32 LSBs on side A; ST1b is the write path for the 32 MSBs for side A. For side B, ST2a is the write path for the 32 LSBs; ST2b is the write path for the 32 MSBs.
Some of the ports for long and double word operands are shared between functional units. This places a constraint on which long or double word operations can be scheduled on a datapath in the same execute packet.
Data Address Paths
Bus 40a has an address bus DA1 which is driven by mux 200a. This allows an address generated by either load/store unit D1 or D2 to provide a memory address for loads or stores for register file 20a. Data Bus LD1 loads data from an address in memory 22 specified by address bus DA1 to a register in load unit D1. Unit D1 may manipulate the data provided prior to storing it in register file 20a. Likewise, data bus ST1 stores data from register file 20a to memory 22. Load/store unit D1 performs the following operations: 32-bit add, subtract, linear and circular address calculations. Load/store unit D2 operates similarly to unit D1, with the assistance of mux 200b for selecting an address.
The DA1 and DA2 resources and their associated data paths are specified as T1 and T2 respectively. T1 consists of the DA1 address path and the LD1a, LD1b, ST1a and ST1b data paths. Similarly, T2 consists of the DA2 address path and the LD2a, LD2b, ST2a and ST2b data paths. The T1 and T2 designations appear in functional unit fields for load and store instructions.
For example, the following load instruction uses the .D1 unit to generate the address but is using the LD2a path resource from DA2 to place the data in the B register file. The use of the DA2 resource is indicated with the T2 designation, for example: LDW .DT2 *A0[3], B1.
Table 3 defines the mapping between instructions and functional units for a set of basic instructions included in a DSP described in U.S. patent application Ser. No. 09/012,813, now U.S. Pat. No. 6,182,203 (incorporated herein by reference). Table 4 defines a mapping between instructions and functional units for a set of extended instructions in an embodiment of the present invention. Alternative embodiments of the present invention may have different sets of instructions and functional unit mapping. Table 3 and Table 4 are illustrative and are not exhaustive or intended to limit various embodiments of the present invention.
The following are examples of what the syntax looks like for the ADD instruction:
1) ADD (.unit) src1, src2, dst
2) ADDU (.unit) src1, src2, dst
3) ADD (.unit) src2, src1, dst
unit=.L1, .L2, .S1, .S2, .D1, .D2
src and dst indicate source and destination respectively. The (.unit) dictates which functional unit the instruction is mapped to (.L1, .L2, .S1, .S2, .Ml, .M2, .D1, or .D2). This instruction has three opcode map fields: src1, src2, and dst.
The addressing modes for instructions that access memory may be linear or circular. The mode is specified by an addressing mode register (AMR) contained in control register file 102. Eight registers can perform circular addressing. A4-A7 are used by the .D1 unit and B4-B7 are used by the .D2 unit. No other units can perform circular addressing modes. For each of these registers, the AMR specifies the addressing mode.
All instructions can be conditional. The condition is controlled by a 3-bit (creg) field specifying a register to be tested, and a 1-bit field (z) specifying a test for zero or nonzero, as shown in
The DSP's opcode map is shown in
Note:
x is don't care for reserved cases.
Instructions are always fetched eight at a time. This constitutes a fetch packet. The execution grouping of the fetch packet is specified by the p-bit, bit zero, of each instruction. Fetch packets are 8-word aligned.
The p bit controls the parallel execution of instructions. The p bits are scanned from left to right (lower to higher address). If the p bit of instruction i is 1, then instruction i+1 is to be executed in parallel with (in the same cycle as) instruction i. If the p-bit of instruction i is 0, then instruction i+1 is executed in the cycle after instruction i. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. All instructions in an execute packet must use a unique functional unit.
Pipeline Operation
The DSP pipeline has several key features which improve performance, decrease cost, and simplify programming. They are: increased pipelining eliminates traditional architectural bottlenecks in program fetch, data access, and multiply operations; control of the pipeline is simplified by eliminating pipeline interlocks; the pipeline can dispatch eight parallel instructions every cycle; parallel instructions proceed simultaneously through the same pipeline phases; sequential instructions proceed with the same relative pipeline phase difference; and load and store addresses appear on the CPU boundary during the same pipeline phase, eliminating read-after-write memory conflicts.
A multi-stage memory pipeline is present for both data accesses and program fetches. This allows use of high-speed synchronous memories both on-chip and off-chip, and allows infinitely nestable zero-overhead looping with branches in parallel with other instructions.
There are no internal interlocks in the execution cycles of the pipeline, so a new execute packet enters execution every CPU cycle. Therefore, the number of CPU cycles for a particular algorithm with particular input data is fixed. If during program execution, there are no memory stalls, the number of CPU cycles equals the number of clock cycles for a program to execute.
Performance can be inhibited by stalls from the memory system, stalls for cross path dependencies, or interrupts. The reasons for memory stalls are determined by the memory architecture. Cross path stalls are described in detail in U.S. patent Ser. No. 09/702,453, filed Oct. 31, 2000, to Steiss, et al and is incorporated herein by reference. To fully understand how to optimize a program for speed, the sequence of program fetch, data store, and data load requests the program makes, and how they might stall the CPU should be understood.
The pipeline operation, from a functional point of view, is based on CPU cycles. A CPU cycle is the period during which a particular execute packet is in a particular pipeline stage. CPU cycle boundaries always occur at clock cycle boundaries; however, stalls can cause CPU cycles to extend over multiple clock cycles. To understand the machine state at CPU cycle boundaries, one must be concerned only with the execution phases (E1-E5) of the pipeline. The phases of the pipeline are shown in
†This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction will not write any results or have any pipeline operation after E1.
Referring again to
The execution of instructions can be defined in terms of delay slots, as shown in Table 7. A delay slot is a CPU cycle that occurs after the first execution phase (E1) of an instruction in which results from the instruction are not available. For example, a multiply instruction has 1 delay slot, this means that there is 1 CPU cycle before another instruction can use the results from the multiply instruction.
Single cycle instructions execute during the E1 phase of the pipeline. The operand is read, operation is performed and the results are written to a register all during E1. These instructions have no delay slots.
Multiply instructions complete their operations during the E2 phase of the pipeline. In the E1 phase, the operand is read and the multiply begins. In the E2 phase, the multiply finishes, and the result is written to the destination (dst) register. Multiply instructions have 1 delay slot.
Load instructions have two results: data loaded from memory and address pointer modification.
Data loads complete their operations during the E5 phase of the pipeline. In the E1 phase, the address of the data is computed. In the E2 phase, the data address is sent to data memory. In the E3 phase, a memory read is performed. In the E4 stage, the data is received at the CPU core boundary. Finally, in the E5 phase, the data is loaded into a register. Because data is not written to the register until E5, these instructions have 4 delay slots. Because pointer results are written to the register in E1, there are no delay slots associated with the address modification.
Store instructions complete their operations during the E3 phase of the pipeline. In the E1 phase, the address of the data is computed. In the E2 phase, the data address is sent to data memory. In the E3 phase, a memory write is performed. The address modification is performed in the E1 stage of the pipeline. Even though stores finish their execution in the E3 phase of the pipeline, they have no delay slots and follow the following rules (i=cycle):
1) When a load is executed before a store, the old value is loaded and the new value is stored.
2) When a store is executed before a load, the new value is stored and the new value is loaded.
3) When the instructions are in are in parallel, the old value is loaded and the new value is stored.
Byte Intermingling Instructions
The DSP of
In order to simplify manipulation of the packed data, a set of byte intermingling instructions is provided. This set of instructions is described in Table 9.
Referring still to
As with all of the instructions executed by the DSP of
Each of the other byte intermingling instructions described in Table 9 operates in a similar manner to select fields from a selected pair of source operands and intermingle the selected fields in an order in accordance with each one of the set of byte intermingling instructions.
Table 11 summarizes the byte ordering of the various destination operands formed by the set of byte intermingling instructions of this embodiment of the present invention.
Multiplexer block 702 provides byte intermingling and will be described in more detail with reference to
Left Most Bit Detection (LMBD) block 704 performs leftmost bit detection in src2 or long_src and src2 as specified by src1. First Adder block 706 performs 40-bit arithmetic using long_src and src2 and sign extended src1. Second Adder block 708 performs multi-field arithmetic on packed data fields in src1 and src2.
Long mux 710 selects from either the long_src LNG or the eight msbs ADD1(39:32) output from 40-bit adder 706 to odd-destination mux 720. Other mux 712 selects from the outputs of logic block 700, mux block 702, LMBD block 704, first adder block 706, second adder block 708 and src1. Other mux 712 is divided into four 8-bit sub-blocks that can each be controlled to select respective portions of the six sets of inputs.
Odd destination mux 720 selects from the outputs of a scan register SCAN31:0 (not shown), the first adder 706 bits ADD1(31:0), long mux 710, other mux 712 and zeros or ones. Odd mux 720 is divided into three separately controlled sections for bits 31:16, 15:8 and 7:0. Even destination register 722 selects from the outputs of a scan register SCAN31:0 (not shown), the first adder 706 bits ADD1(31:0), other mux 712 and zeros or ones. Even mux 722 is divided into two separately controlled sections for bits 31:16 and 15:0.
Thus, the intermingling circuit forms a intermingled destination operand corresponding to a selected number of fields from a selected pair of source operands that are then written into respective field positions of a selected destination register during instruction pipeline E1 in response to a single byte intermingling instruction.
One skilled in the art will recognize that intermingling circuitry 702 may be implemented in a number of different ways, by using various configurations of multiplexers, shifters, barrel shifters, and such. In another embodiment, the intermingling circuitry may be implemented such that a multi-field byte intermingling instruction executes with a different number of delay slots, such as one or two, for example. In another embodiment, a bit field having a different width may be intermingled, such as four for example. There may be other varieties of intermingling instructions wherein different opcodes or a parameter is used to identify various bit field widths. In this embodiment of the present invention, intermingling circuitry is included in the L and S units of the CPU. However, in another embodiment, intermingling circuitry may be included in other or different functional units.
In another embodiment of the invention, an intermingled destination operand may be written directly to memory rather to a register file. This is described in more detail in Co-assigned U.S. patent application Ser. No. 09/687,540 entitled Data Processing System with Register Store/Load Utilizing Data Packing/Unpacking and is incorporated herein by reference.
EMIF 1052 provides a 16-bit interface for access to external peripherals, not shown. Expansion bus 1070 provides host and I/O support similarly to host port 60/80 of
Three multi-channel buffered serial ports (McBSP) 1060, 1062, 1064 are connected to DMA controller 1040. A detailed description of a McBSP is provided in U.S. patent Ser. No. 09/055,011, now U.S. Pat. No. 6,167,466 and is incorporated herein by reference.
Fabrication of digital system 10 involves multiple steps of implanting various amounts of impurities into a semiconductor substrate and diffusing the impurities to selected depths within the substrate to form transistor devices. Masks are formed to control the placement of the impurities. Multiple layers of conductive material and insulative material are deposited and etched to interconnect the various devices. These steps are performed in a clean room environment.
A significant portion of the cost of producing the data processing device involves testing. While in wafer form, individual devices are biased to an operational state and probe tested for basic operational functionality. The wafer is then separated into individual dice which may be sold as bare die or packaged. After packaging, finished parts are biased into an operational state and tested for operational functionality.
Thus, a digital system is provided with a processor having an improved instruction set architecture. The processor is code-compatible with C62xx DSP processors from Texas Instruments Incorporated. It provides a superset of the C62x architecture while providing complete code compatibility for existing C62x code. The processor provides extensions to the existing C62x architecture in several areas: register file enhancements, data path extensions, additional functional unit hardware, increased orthogonality of the instruction set, data flow enhancements, 8-bit and 16-bit extensions, and additional instructions that reduce code size and increase register flexibility.
Advantageously, a set of multi-field byte intermingling instructions is provided that provides features of single instruction, multiple data (SIMD) operation. Code size is thereby reduced and performance improved.
As used herein, the terms “applied,” “connected,” and “connection” mean electrically connected, including where additional elements may be in the electrical connection path. “Associated” means a controlling relationship, such as a memory resource that is controlled by an associated port. The terms assert, assertion, de-assert, de-assertion, negate and negation are used to avoid confusion when dealing with a mixture of active high and active low signals. Assert and assertion are used to indicate that a signal is rendered active, or logically true. De-assert, de-assertion, negate, and negation are used to indicate that a signal is rendered inactive, or logically false.
While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. In another embodiment, the source operands may be provided in response to a memory fetch instead of being read from the register file. An intermingling instruction may be executed in another functional unit instead of or in addition to the .L or .S functional units. In another embodiment, a different number of fields, such as eight, for example, could be intermingled. Different opcodes could define the number of fields, or a parameter could define the number of fields, for example.
In another embodiment, fewer byte intermingling instructions may be provided. Conversely, additional selections of byte intermingling may be provided.
In another embodiment, a control register is provided that is loaded with a control word to control the operation of a set of multiplexors and thereby provide a set of multi-field byte intermingling operations that provides features of single instruction, multiple data (SIMD) operation. For example, four bits are allocated in the control register for each byte of the destination. Using the four bits, any byte from any position of the source operands with up to sixteen options can be selected. Therefore, an eight byte destination can be completely specified using a 32-bit control register such that each byte of the destination can receive any byte from eight byte of a source operand, and additionally specify sign-extension, fill with zeros, fill with ones, and leave an original destination byte unaltered to form a merge, for example.
In another embodiment, the various fields overlap each other, such that the result for each field includes bits included within another field.
In another embodiment, values in each field could be treated as something other than an unsigned value, such as a signed value, or a floating point value, for example.
It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.
This application is a divisional of application Ser. No. 09/702,405, filed Oct. 31, 2000, which claims priority under 35 USC §119(e)(1) of Provisional Application No. 60/183,527, filed Feb. 18, 2000 and of Provisional Application No. 60/173,761, filed Dec. 30, 1999; and which is related to copending application Ser. No. 09/703,096 filed Oct. 31, 2000, which claims priority of Provisional Application No. 60/183,527; and which is related to copending application Ser. No. 09/687,540 filed Oct. 13, 2000, which claims priority of Provisional Application No. 60/173,761.
| Number | Date | Country | |
|---|---|---|---|
| 60183527 | Feb 2000 | US | |
| 60173761 | Dec 1999 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09702405 | Oct 2000 | US |
| Child | 11114549 | Apr 2005 | US |
