Claims
- 1. A microprocessor for performing both graphics and non-graphics operations, comprising:a source register; and divide and square-root logic having an input coupled to said source register and to a pipeline bus said divide and square root logic configured to determine the value of one divided by the square root of each of a plurality of values in said source register in parallel; and a floating point graphics multiply unit coupled to the pipeline bus.
- 2. The microprocessor of claim 1 wherein said divide and square-root logic comprises a look-up table.
- 3. The microprocessor of claim 1 wherein said divide and square-root logic comprises iterative logic.
- 4. The microprocessor of claim 1, further comprising:a floating point graphics arithmetic logic unit coupled to the pipeline bus.
- 5. The microprocessor of claim 4, further comprising:a graphics status register coupled to both the floating point graphics arithmetic logic unit and the floating point graphics multiply unit.
- 6. A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising:an OPcode instruction configured to cause said microprocessor to perform a determination of the value of one divided by the square-root of each of a plurality of partitioned fields of an input source register in parallel; and an OPcode instruction configured to cause said microprocessor to perform a plurality of graphics data packing instructions.
Parent Case Info
This application is a division of and claims the benefit of U.S. application Ser. No. 09/417,874, filed Oct. 13, 1999, now abandoned which is a divisional of U.S. application Ser. No. 08/722,442, filed Oct. 10, 1996, now issued U.S. Pat. No. 5,996,066 the disclosure of which are incorporated by reference.
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