Patent Application
20190103320
This invention relates generally to field-effect transistors (FETs), and more particularly to reducing gate to drain capacitance in metal-oxide semiconductor field-effect transistors (MOSFETs) for integrated circuits (ICs).
Metal-oxide semiconductor field-effect transistors (MOSFETs) are valuable components in many high input impedance or high gain circuits, high speed switching circuits, or radio frequency (RF) integrated circuits (ICs) that are used, for example, in set top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, mobile phones, cellular phones, smart phones, tablets, phablets, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, and automobiles. The benefit of power MOSFETs include generally high switching speeds and a relatively low on-resistance.
Shielded gate MOSFETs are preferred because they provide reduced gate-to-drain capacitance, reduced on-resistance, and increased breakdown voltage of the transistor. By shielding the gate from the electric field in the drift region, the shielded gate MOSFET structure substantially reduces the gate-to-drain capacitance. The shielded gate MOSFET structure also provides the added benefit of higher minority carrier concentration in the drift region for the device's breakdown voltage and hence lower on-resistance
A conventional way of shielding a gate MOSFET is to fabricate a Tungsten Silicide (WSi) Faraday shield between the gate and the underlying drain. Fabrication of the WSi Faraday shield, however, requires an additional polysilicon deposition, mask, and etch. These additional steps add costs, require additional specification, and may add defects to the IC. As such, there is a need for an apparatus and process for fabricating a shielded gate MOSFET in an IC that reduces costs and steps in process flow, and that still provides effective reduction of gate to drain parasitic capacitance.
Aspects disclosed herein include middle-of-line (MOL) shield gates in integrated circuits (ICs). In this regard, in certain aspects disclosed herein, one or more metal resistors are fabricated in a MOL layer of an IC to shield the IC. The MOL layer is formed above and adjacent to an active semiconductor area in a front-end-of-line (FEOL) portion of the IC that includes devices, e.g., MOSFETS. The metal resistor(s) can be coupled through contacts formed in the MOL layer to interconnect lines in interconnect layer(s) so as to be coupled, for example, to a voltage source, on-chip RF, and/or power circuit in the IC.
Thus, by fabricating a metal resistor in the MOL layer in the IC, the metal resistor can advantageously be localized very close to semiconductor devices, such as transistors, to more accurately shield the semiconductor devices. Also, by providing the metal resistor in the MOL layer, the same fabrication processes used to create contacts in the MOL layer can also be used to fabricate the metal resistor in the MOL layer. Further, because the MOL layer is already provided in the IC to provide contacts between the semiconductor devices in the active semiconductor layer and the interconnect layers, additional area may not be required to provide the metal resistors in the IC.
With reference to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Because metal resistor 106 is disposed in MOL layer 108 immediately above and/or adjacent to active semiconductor layers 112 in this example, metal resistor 106 in MOL layer 108 can advantageously be localized very close to semiconductor devices in active semiconductor layers 112, such as FinFET 120, to more effectively reduce gate to drain parasitic capacitance.
To provide connectivity to MOL shielded gate 104 and direct voltage Vss to metal resistor 106, a first contact 126(1) is provided in MOL layer 108. First contact 126(1) is electrically coupled to a contact area 128 of metal resistor 106. For example, first contact 126(1) may be conductive contact pad made out of a Tungsten (W) material. In this example, first contact 126(1) physically contacts contact area 128. First and second vertical interconnect accesses ViasO (VOs) 130(1), 130(2) are fabricated in an interconnect layer 132 in an interconnect area 134 of semiconductor die 100 in aligned contact with first and second contacts 126(1), 126(2). For example, interconnect layer 132 is shown as a metal 1 (M1) layer directly above MOL layer 108. First and second interconnects 136(1), 136(2) are formed in interconnect layer 132 above and in contact with first and second VOs 130(1), 130(2). For example, first and second interconnects 136(1), 136(2) may be metal lines 138(1), 138(2) that were fabricated from a conductive material disposed in trenches formed in a dielectric material 141. In this manner, connectivity to MOL shielded gate 104 is provided through metal lines 138(1), 138(2) in this example.
Thus, by fabricating metal resistor 106 in MOL layer 108 in IC 102, metal resistor 106 can advantageously be localized and very close to semiconductor devices in active semiconductor layers 112, to effectively reduce gate to drain parasitic capacitance. For example, MOL layer 108 may have a thickness T of approximately eighteen (18) nanometers (nm) or less, which may be a thickness ratio of approximately 0.26 or less to the thickness of semiconductor layers 112. Further, because MOL layer 108 is already provided in IC 102 to provide contacts between semiconductor devices in the semiconductor layers 112 and interconnect layer 132 including, e.g., first and second semiconductor layer contacts 150(1), 150(2), additional area may not be required to provide metal resistor 106 in IC 102. For example, metal resistor 106 may have approximately a width/length (W/L) of 0.21 μm/0.21 μm.
Metal resistor 106 can be formed from any conductive material. As examples, metal resistor 106 can be formed from Tungsten Silicide (WSi), Titanium Nitride (TiN), and Tungsten (W). Metal resistor 106 should have a sufficient resistance to be sensitive to changes in ambient temperature. For example, the resistance of metal resistor 106 may be at least 400 ohms per W/L μm of semiconductor devices. Also, by disposing metal resistor 106 in MOL layer 108, it may be efficient from a fabrication process standpoint to form metal resistor 106 from the same material as a work function material 140 disposed adjacent to gate (G) 124 of FinFET 120.
As illustrated in processing stage 300(1) in
Next, a MOL layer 308 is formed above active semiconductor layer 312 (block 208 in
Next, as shown in a second process stage 300(2) in
Next, as shown in process stage 300(6) in
MOL shielded gates in integrated circuits (ICs), and according to any of the examples disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include set top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, mobile phones, cellular phones, smart phones, tablets, phablets, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, and automobiles.
In this regard,
Other devices can be connected to the system bus 410. As illustrated in
The CPU 402 may also be configured to access the display controller(s) 424 over the system bus 410 to control information sent to one or more displays 428. The display(s) 428 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. The display controller(s) 424 sends information to the display(s) 428 to be displayed via one or more video processors 430, which process the information to be displayed into a format suitable for the display(s) 428.
A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device 500 in
In the transmit path, the data processor 508 processes data to be transmitted and provides I and Q analog output signals to the transmitter 510. In the exemplary wireless communications device 500, the data processor 508 includes digital-to-analog-converters (DACs) 514(1) and 514(2) for converting digital signals generated by the data processor 508 into the I and Q analog output signals, e.g., I and Q output currents, for further processing.
Within the transmitter 510, lowpass filters 516(1), 516(2) filter the I and Q analog output signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (AMP) 518(1), 518(2) amplify the signals from the lowpass filters 516(1), 516(2), respectively, and provide I and Q baseband signals. An upconverter 520 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers 524(1), 524(2) from a TX LO signal generator 522 to provide an upconverted signal 526. A filter 528 filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) 530 amplifies the upconverted signal from the filter 528 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 532 and transmitted via an antenna 534.
In the receive path, the antenna 534 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 532 and provided to a low noise amplifier (LNA) 536. The duplexer or switch 532 is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA 536 and filtered by a filter 538 to obtain a desired RF input signal. Downconversion mixers 540(1), 540(2) mix the output of the filter 538 with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 542 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMP) 544(1), 544(2) and further filtered by lowpass filters 546(1), 546(2) to obtain I and Q analog input signals, which are provided to the data processor 508. In this example, the data processor 508 includes analog-to-digital-converters (ADCs) 548(1), 548(2) for converting the analog input signals into digital signals to be further processed by the data processor 508.
In the wireless communications device 500 in
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
