The present invention relates generally to power converters, and more specifically the modulation of a jitter signal in a controller.
Electronic devices (such as cell phones, tablets, laptops, etc.) use power to operate. Switched mode power converters are commonly used due to their high efficiency, small size, and low weight to power many of today's electronics. Conventional wall sockets provide a high voltage alternating current. In a switching power converter, a high voltage alternating current (ac) input is converted to provide a well-regulated direct current (dc) output through an energy transfer element to a load. In operation, a switch is turned ON and OFF to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of on/off pulses per unit time of the switch in a switched mode power converter.
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.
Examples power converter including a controller with a switch controller with a jitter generator are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
To illustrate,
The example switched mode power converter 100 illustrated in
The power converter 100 provides output power to the load 126 from an unregulated input voltage. In one embodiment, the input voltage is the ac input voltage VAC 102. In another embodiment, the input voltage is a rectified ac input voltage such as rectified voltage VRECT 106. The rectifier 104 outputs rectified voltage VRECT 106. In one embodiment, rectifier 104 may be a bridge rectifier. The rectifier 104 further couples to the energy transfer element T1114. In some embodiments of the present invention, the energy transfer element T1114 may be a coupled inductor. In other embodiments, the energy transfer element T1114 may be a transformer. In a further example, the energy transfer element T1114 may be an inductor. In the example of
In addition, the clamp circuit 110 is illustrated in the example of
Secondary winding 116 of the energy transfer element T1114 is coupled to the rectifier D1118. In the example of
The power converter 100 further comprises circuitry to regulate the output, which is exemplified as output quantity UO 128. In general, the output quantity UO 128 is either an output voltage VO 124, an output current IO 122, or a combination of the two. A sense circuit 130 is coupled to sense the output quantity UO 128 and to provide feedback signal UFB 131, which is representative of the output quantity UO 128. Feedback signal UFB 131 may be a voltage signal or a current signal. In one example, the sense circuit 130 may sense the output quantity UO 128 from an additional winding included in the energy transfer element T1114.
In another example, there may be a galvanic isolation (not shown) between the controller 132 and the sense circuit 130. The galvanic isolation could be implemented by using devices such as an opto-coupler, a capacitor or a magnetic coupling. In a further example, the sense circuit 130 may utilize a voltage divider to sense the output quantity UO 128 from the output of the power converter 100.
Switch controller 138 is coupled to the sense circuit 130 and receives the feedback signal UFB 131 from the sense circuit 130. Switch controller 138 further includes terminals for receiving the current sense signal 136, and provides a drive signal UD 144 to power switch S1134. The current sense signal 136 may be representative of the drain current ID 142 in the power switch S1134. Current sense signal 136 may be a voltage signal or a current signal. In addition, switch controller 138 provides drive signal UD 144 to the power switch S1134 to control various switching parameters to control the transfer of energy from the input of power converter 100 to the output of power converter 100. Examples of such parameters may include switching frequency, switching period, duty cycle, or respective ON and OFF times of the power switch S1134. As shown in the depicted example, the jitter generator 140 is coupled to receive a drive signal UD 144 from the switch controller 138 and generate a jitter signal UJTR 141.
In operation, the jitter signal UJTR 141 is modulated as switching frequency approaches the jitter frequency. In one example, the modulation is a frequency modulation whereby the frequency of the jitter signal is changed, and the amplitude remains the same. Further explanation of how the jitter signal UJTR 141 is modulated will be explained in
Comparator 248 includes a first input coupled to one end of the capacitor CJTR 258, and a second input is coupled to a voltage reference. In one example, the voltage reference is a first voltage reference VREF_T 263 or a second voltage reference VREF_B 264. The value of the voltage reference is selected in response to the output of the comparator 248.
The jitter generator circuit 240 further includes a first logic gate 260 having a first input is coupled to an inverted output of the comparator 248, and a second input coupled to the hold signal UH 265 of the timer circuit 246. In one example, the hold signal UH 265 is an active low signal. The first logic gate 260 is coupled to activate or deactivate a second switch 255 coupled current source ICHG 250 to charge the capacitor CJTR 258. A second logic gate 261 having a first input is coupled to the output of the comparator 248, and a second input is coupled to the hold signal UH 265. The second logic gate 261 is coupled to activate or deactivate a third switch 257 coupled to current source IDIS 252 to discharge capacitor CJTR 258.
In operation, the comparator 248 determines if the jitter signal UJTR 241 is greater than either a first voltage reference VREF_T 263 or a second voltage reference VREF_B 264. The capacitor CJTR 258 is coupled to be charged by a first current source ICHG 250 if the jitter signal UJTR 241 is less than a first voltage reference VREF_T 263, and the capacitor CJTR 258 is coupled to be discharged by a second current source IDIS 252 if the jitter signal UJTR 241 is greater than a second voltage reference VREF_B 264. The hold signal UH 265 generated by timer circuit 265 is coupled to cease the charging of the capacitor CJTR 258 when a pulse of the drive signal UD 244 has been detected at a frequency below a defined threshold frequency FTH, or cease the discharging of the capacitor CJTR 258 when a pulse of the drive signal UD 244 has been detected below a defined threshold frequency FTH. A logic high of timer circuit 246 indicates the timer has not expired, while a logic low timer circuit indicates the timer has expired.
The discharge signal UDCH 262 is coupled to switch 267 to couple the second voltage reference to the inverting input of comparator 248. Furthermore, the discharge signal is coupled to an input of logic gate 261 that opens and closes the third switch S3257 that discharges the capacitor CJTR 258. The timer circuit 246 is coupled to generate the hold signal UH 265 in response to the drive signal UD 244 to indicate whether a pulse of the drive signal UD 244 has been detected at a frequency below a first threshold frequency, which in one example can be known as a defined threshold frequency FTH.
In addition, the discharge signal UDCH 248 is coupled to inverter 266 to generate a charge signal UCH 259. The charge signal UCH 259 is coupled to the switch 268, to couple the first voltage reference to the inverting input of comparator 248. The charge signal UCH 259 is coupled to an input of logic gate 260 that opens and closes the second switch S2255 that charges the capacitor CJTR 258. When the jitter signal UJTR 241 is greater than a first voltage reference VREF_T 263, the discharge signal UDCH 262 transitions to a logic high. The inverter 266 transitions the charge signal UCH 259 to a logic low, and logic gate 260 opens switch 255. The charge signal UCH 259 also opens the fifth switch 268. The discharge signal UDCH 262 closes the fourth switch 267 that is coupled to the second voltage reference VREF_B 264. Logic gate 261 is coupled to receive the discharge signal UDCH 262 and the hold signal UH 265. The third switch 257 is closed in response to logic gate 261.
As shown in the example of
One input of the comparator 380 is coupled to one end of capacitor CP2 378, and the other input of comparator 380 is coupled to a voltage reference VREF 377. In the beginning of every switching cycle, the capacitor CP2 378 is completely discharged.
In operation, the one shot circuit 381 is coupled to receive the drive signal UD 344. The output of the one-shot circuit 381 is coupled to inverter 370, which opens and closes switch 379. When the switch 379 is OFF, switch 372 is ON and the capacitor CP2 378 is discharged to local return 356. The capacitor CP2 378 should be completely discharged prior to switch 379 turning ON. When switch 379 is ON and switch 372 is OFF, current source 376 with a voltage potential VP 374 charges the capacitor CP2 378. The size of capacitor CP2 378 and/or value of current source 376, and/or the value of voltage VREF 377 may be selected to a fixed time period TFTH that corresponds with the defined threshold frequency FTH. The hold signal UH 365 transitions to a logic low when the voltage of the capacitor CP2 378 exceeds a voltage reference VREF 377.
In another example, timer circuit 346 can be implemented as a digital circuit instead of an analog circuit as described previously. The timer circuit 346 would include a digital counter with a clock input.
In one example, the jitter signal waveform can be a triangle waveform. In other examples, the jitter signal waveform can be a sawtooth waveform. In a further example, the jitter signal waveform is a periodic waveform. In general, the modulated jitter signal has the same amplitude as the original jitter signal, and a slower frequency. The modulated jitter signal UJTR 441 can be used to adjust parameters such as variable current limit, frequency, on time TON, and off time TOFF. During time t1 to time t2, the jitter generator generates a jitter signal with a positive slope as seen in the timing diagram for a charge time tCH 482. The timer circuit generates a logic high for hold signal UH 465. The charge signal UCH 459 is logic high when the voltage of the capacitor CJTR is less than a first threshold reference VREF_T. The discharge signal UDCH 462 is logic low. At time t2 to time t3, the hold signal UH 465 transitions to a logic low for a hold time tH 486. The jitter signal UJTR 441 includes a flat or zero slope for a hold time tH 486. Although the charge signal UCH 459 is a logic high, the hold signal UH 465 holds charging of the jitter signal UJTR 441. In other words, the hold signal UH 465 gates the charge signal UCH 459 from propagating. In one example, the charge time tCH 582 and the hold time tH 486 are not identical. The hold time tH 486 may vary as the difference between switching period versus the threshold period. The discharge signal UDCH 462 is logic low.
During time t4 to time t5, the jitter generates a jitter signal with a negative slope for a discharge time tDCH 488. The timer circuit generates a logic high signal of hold signal UH 465. The discharge signal UDCH 462 is a logic high when the voltage UJTR 444 of the capacitor CJTR of the jitter generator is greater than a second threshold reference VREF_B. The charge signal UCH 459 is logic low. At time t5 to time t6, the hold signal transitions to a logic low for a hold time tH 486. In one example, the hold time after a charging time is equivalent to the hold time after a discharging charging time. In another example, the charge and discharge times are equivalent and while the hold times can vary. The jitter signal UJTR 441 is flat with a zero slope during the hold time tH 486. Although the discharge signal UDCH 462 is a logic high, the hold signal UH 465 holds charging of the jitter signal UJTR 441. In one example, the discharge time tDCH 488 and the hold time tH 486 may vary with respect to each other. The charge signal UCH 459 is a logic low.
At time t7 to time t8, the positive slope of the jitter signal UJTR 441 is equivalent to what was described during time t1 to time t2. At time t8 to time t9, the flat slope of the jitter signal 441 is equivalent to what was described during time t2 to time t3. At time t10 to time t11, the negative slope of the jitter signal UJTR 441 is equivalent to what was described during time t4 to time t5. At time t11 to time t12, the flat slope of the jitter signal UJTR 441 is equivalent to what was described at time t5 to time t6.
Process 600 begins at the start block 602 and continues to decision block 604. At decision block 604, a drive signal must be received. If the drive signal is not received, process 600 proceeds to decision block 608. If the drive signal is received, process 600 proceeds to block 606. At block 606, the timer circuit is restarted and enabled. Process 600 loops to decision block 604.
If the drive signal was not received at decision block 604 and process 600 continued to decision block 608 as mentioned previously, the current status of the timer is checked at decision block 608. If the timer is not expired, process 600 proceeds to block 610 and charges or discharges the capacitor of the jitter generator. Process 600 then loops back to decision block 604 then to decision block 608 until the timer expires. Once the timer expires as checked at decision block 608, process 600 proceeds to block 612. At block 612, a hold signal to charge/discharge the capacitor of the jitter generator is enabled. Process 600 then loops back to decision block 604.
Controller 732 is further illustrated as including the primary controller 733 and the secondary controller 792 with a communication link 798 between the primary controller 733 and the secondary controller 792. In one example, the primary controller 733 and secondary controller 792 could be formed as a monolithic circuit. As illustrated, the primary controller 733 further includes a jitter generator circuit 740 and a switch controller 738 as shown in the previous figures. The secondary controller 792 is coupled to generate a secondary control signal 796 coupled to be received by the synchronous rectifier circuit 721 to rectify the output of the power converter.
In another example, the jitter generator 740 may be implemented on the secondary controller 792 instead of the primary controller 733 to produce the same effect on the output switching frequency.
The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.
These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.
This application is a continuation of U.S. application Ser. No. 16/129,251, filed on Sep. 12, 2018, which is a continuation of U.S. application Ser. No. 15/631,998 filed Jun. 23, 2017, now U.S. Pat. No. 10,088,854, which issued on Oct. 2, 2018, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application No. 62/395,942, filed on Sep. 16, 2016, which is incorporated herein by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
6107851 | Balakrishnan et al. | Aug 2000 | A |
6249876 | Balakrishnan et al. | Jun 2001 | B1 |
6980441 | Man-Ho | Dec 2005 | B2 |
7425834 | Matthews et al. | Sep 2008 | B2 |
7671486 | Yang | Mar 2010 | B2 |
7778050 | Yamashita | Aug 2010 | B2 |
8368370 | Moorish | Feb 2013 | B2 |
8437152 | Sato et al. | May 2013 | B2 |
8611116 | Baurle et al. | Dec 2013 | B2 |
8730687 | Yang et al. | May 2014 | B2 |
8766561 | Esaki et al. | Jul 2014 | B2 |
8970260 | De Haas | Mar 2015 | B1 |
8994276 | Recker et al. | Mar 2015 | B2 |
9036377 | Chang et al. | May 2015 | B2 |
9065427 | Kleinpenning | Jun 2015 | B2 |
9077249 | Tsou et al. | Jul 2015 | B2 |
9246392 | Balakrishnan et al. | Jan 2016 | B2 |
9277604 | Hsia et al. | Mar 2016 | B2 |
9450478 | Djenguerian et al. | Sep 2016 | B1 |
9774248 | Saint-Pierre et al. | Sep 2017 | B2 |
9787196 | Wang | Oct 2017 | B2 |
9876433 | Pregitzer et al. | Jan 2018 | B2 |
10205394 | Pham et al. | Feb 2019 | B2 |
10585444 | Pham | Mar 2020 | B2 |
20100302816 | Hu et al. | Dec 2010 | A1 |
20110175584 | Huber et al. | Jul 2011 | A1 |
20120194227 | Lin et al. | Aug 2012 | A1 |
20120300499 | Chang et al. | Nov 2012 | A1 |
20130027990 | Baurle et al. | Jan 2013 | A1 |
20130088206 | Tsou et al. | Apr 2013 | A1 |
20130106379 | Morrish | May 2013 | A1 |
20130182469 | Chiang | Jul 2013 | A1 |
20130194227 | Chang | Aug 2013 | A1 |
20130300499 | Sharawi | Nov 2013 | A1 |
20140085936 | Jin et al. | Mar 2014 | A1 |
20140268911 | Telefus | Sep 2014 | A1 |
20150280659 | Yuan et al. | Oct 2015 | A1 |
20160134186 | Saint-Pierre et al. | May 2016 | A1 |
20160268901 | Nishijima | Sep 2016 | A1 |
20170085185 | Wang | Mar 2017 | A1 |
20180083540 | Pham et al. | Mar 2018 | A1 |
20190348910 | Chou | Nov 2019 | A1 |
Number | Date | Country |
---|---|---|
2877127 | Mar 2007 | CN |
101174796 | May 2008 | CN |
102790529 | Nov 2012 | CN |
102904446 | Jan 2013 | CN |
102594154 | Aug 2014 | CN |
105226953 | Jan 2016 | CN |
101610024 | Dec 2019 | CN |
2779402 | Sep 2014 | EP |
2779402 | Oct 2017 | EP |
H02266269 | Oct 1990 | JP |
2008312399 | Dec 2008 | JP |
2009142085 | Jun 2009 | JP |
2010245675 | Oct 2010 | JP |
Entry |
---|
““India Office Action No. 201714031549, dated Oct. 22, 2019”, 6 pages”, 1-6. |
“European Search Report Application No. 17191404.7-1201, dated Mar. 26, 2019”, 9 pages. |
“Power Integrations: “Application Note AN-59 LYTSwitch-4 Family (Revision A)””, Dec. 31, 2014. |
“Power Integrations: “Application Note AN-61 Linkswitch-3 Family Design Guide and Considerations””, Apr. 30, 2015. |
Chinese Search Report; Application No. 201710832719.5; dated Nov. 5, 2020; 3 pages. |
First Chinese Office Action; Application No. 201710832719.5; dated Nov. 13, 2020; 5 pages. |
Machine Translation of Chinese Search Report; Application No. 201710832719.5; dated Nov. 5, 2020; 3 pages. |
Machine Translation of First Chinese Office Action; Application No. 201710832719.5; dated Nov. 13, 2020; 11 pages. |
European Communication Pursuant to Article 94(3) EPC; Application No. 17191404.7; dated Dec. 11, 2020; 14 pages. |
European Patent Application No. 17191404.7-Extended European Search Report dated Feb. 23, 2018, 9 pages. |
Japanese Office Action; Application No. 2017175201; dated Apr. 20, 2021; 6 pages. |
Machine Translation of Japanese Office Action and Search Report; Application No. 2017-175201; dated Apr. 20, 2021; 19 pages. |
Number | Date | Country | |
---|---|---|---|
20200218298 A1 | Jul 2020 | US |
Number | Date | Country | |
---|---|---|---|
62395942 | Sep 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 16129251 | Sep 2018 | US |
Child | 16792128 | US | |
Parent | 15631998 | Jun 2017 | US |
Child | 16129251 | US |