Patent Application
20090174435
1. Background Discussion
The semiconductor industry is facing very difficult challenges moving forward, as the scaling down of critical dimensions in standard bulk CMOS technologies is harder to achieve due to technical, technological, and economic constraints. Furthermore, even if scaling continues (probably at a slower pace), the resulting devices are likely to exhibit poor characteristics such as slow carrier mobility (slow performance), large off currents (leakage), large process variations, poor reliability, etc. There are several directions that promise to solve, or at least ease, some of the problems associated with scaling. Some of these directions use conventional top-down fabrication techniques (e.g., lithography), but try to obtain device structures that are intrinsically more scalable, such as the dual- and tri-gate devices (e.g., FinFET) investigated at Intel, UC Berkeley, etc., Other directions use novel bottom-up fabrication (i.e., self-assembly), such as Carbon Nano-Tubes (CNT) and molecular electronics, to overcome the limitations of lithography. Recently, there has been much excitement (and industry support) in the research community about the promise of CNTs. CNTs exhibit excellent intrinsic performance, high gain, high carrier mobility, high reliability, and, in general, are intrinsically an almost ideal device.
However, CNTs have several possible fatal flaws, in the fact that there is no clear strategy for arranging multiple such tubes on a substrate, and there is also no clear strategy for controlling the chirality of such CNTs. Most demonstrations until now have consisted of crude circuits obtained by manually selecting and arranging CNTs one by one, which is clearly unacceptable for any practical applications. The few experiments that used in-situ growth of CNTs (see Background references [5] and [51]) have still not shown applicability to general circuit design. On the other hand, the semiconductor industry has invested significantly in planar fabrication techniques, and solutions compatible with current practice are clearly preferable.
2. List of Related Art
The following is a listed of related art that is referred to in and/or forms some of the basis of other sections of this specification. All of these listed references are therefore incorporated by reference in their entirety for all purposes.
An aspect of various embodiments of the present invention comprises, but is not limited to, graphene sheets patterned into ribbons of given widths and at given angles (with respect to the two-dimensional graphene hexagonal lattice). Such graphene nanoribbons (GNRs) have either metallic or semiconductor behavior, depending on their dimensions and orientation to the hexagonal graphene lattice.
A second aspect of various embodiments of the present invention comprises, but is not limited to, using combinations of such GNRs of various dimensions and angles in order to create circuits formed of devices and interconnects that intrinsically have no interface defects as they are pattered from the same two-dimensional graphene sheet.
A third aspect of the present invention provides, among other things, the design of graphene-ribbon circuits in which the devices are arranged in plane such that metallic and semiconductor alternate in order to create the desired circuit behavior. For example, a metallic ribbon can be used as a wire, two semiconductor ribbons in parallel can create an OR function, two in series can create an AND function, etc.
A fourth aspect of various embodiments of the present invention comprises, but is not limited to, the use of various passivating elements at the edges in order to modulate conduction properties, as well as the use of gating structures in order to turn the devices on and off by the use of voltages. The undoped graphene devices are intrinsically ambipolar; however, the desired NMOS- or PMOS-like asymmetric behavior can be obtained by shifting the Fermi level of the channel region by using metals with specific workfunctions for the gate or by doping chemically, electrostatically, or by other means.
A fifth aspect of various embodiments of the present invention is that the principles described herein can be applied to myriad electronic structures such as, but not limited to, multi-ribbon structures alternating metallic and semiconductor behavior in order to obtain combined wire/device structures with no interface defects. Such structures are created by patterning a single planar graphene sheet, a technique that has not been investigated until now. The idea of using different elements for passivating the ribbon edges in order to tune ribbon behavior has also not been investigated until now.
Graphene nanoribbons (GNRs), a term intended in this specification to encompass carbon nanoribbons (CNRs), are essentially a monolayer of graphite patterned into a narrow strip, and have recently been proposed as an attractive alternative to carbon nanotubes (CNTs) (see Background reference [63]). While CNTs have many highly desirable electronic properties (such as exceedingly high mobility and potentially excellent short channel effects in field-effect transistors (FETs) due to a small “depth”/length aspect ratio), no method of assembling large-scale circuits comprised of CNTs has yet been devised. The main difficulty is that CNTs are created prior to integration and need to be placed in correct positions in the circuit. This is contrary to the conventional planar process in silicon, in which devices are formed on the entire wafer at once by lithographic means. GNRs offer the promise of lithographic patternability, while providing electronic properties similar to those of CNTs. Furthermore, the electronic properties of GNRs are lithographically tunable, selecting metallic vs. semiconducting GNRs, by the orientation of the edge termination (for a semiconducting armchair GNR, see
GNRs have electrical characteristics that are quite similar to CNTs (and thus, exhibit good performance). However, being planar, GNRs can be patterned using more standard semiconductor industry fabrication methods. This way, using GNRs can bypass the alignment problem that CNTs face, and in addition, GNRs can control the ribbon orientation (and thus, its metallicity). In contrast, CNT chiralities are predetermined statistically during the manufacture process and have been near impossible to control. This embodiment targets combinations of ribbons of various dimensions, of various orientations, and in various arrangements (thus, behaving as either metal or semiconductor, with or without gating) in order to obtain circuit elements and devices that can be used for more complex circuits, such as logic gates and memory elements.
Graphene, a single sheet of graphite, is a two-dimensional (2D) carbon system arranged in a hexagonal (also known as honeycomb) lattice. The carbon atoms in graphene are sp2 hybridized and have strong links with their three nearest neighbors. The 2pz atomic orbitals (AOs) of adjacent atoms in the graphene sheet overlap and form bonding (π-band) and anti-bonding (π*-band) 2D bands.
The band diagram of the 2D graphene is relevant for understanding CNTs, except that due to the small diameter of the tube, the CNT becomes a quasi one-dimensional system and the energy levels are quantized in the transversal direction. There are many ways in which the graphene sheet can be rolled to form a CNT, but they all can be described by the use of just two numbers. Assume a graphene sheet with the lattice arranged as in
The chiral vector determines the way that the energy levels are quantized in the CNT, and the interaction between this quantization and the energy bands of the graphene determines the electrical characteristics of the CNT.
The bandstructure of GNRs is computed using the conventional nearest neighbor Tight-Binding method, with a pz-orbital-derived Bloch wavefunction basis, similar to the method frequently used for CNTs (see Background references [64] and [65]). The overlap element is retained, resulting in the generalized Eigen problem. The pz basis is sufficient even for narrow ribbons, since the small-curvature approximation usually made for CNTs is strictly valid for GNRs. The absence of curvature implies that the pz portion of the TB Hamiltonian is decoupled from the sp2 in-plane part, and can be treated separately. Since the bottom of the conduction band and the top of the valence bands are formed using precisely the pz set of states, which are in turn decoupled from the rest of the Hamiltonian, only the pz portion is used for computations. The key ingredient for GNR computation is the treatment of the boundary conditions. Whereas the CNT has periodic boundary conditions in both the transport and “width” directions, the GNR has periodic boundary conditions only in the transport direction. No special boundary condition is asserted on the wavefunctions in the transverse directions; the edge atoms are simply assumed to have fewer coupling neighbors. In order to facilitate computations with this boundary condition, the zone-folding approach is not used, resulting in a larger (but still quite manageable) Eigenvalue problem. Note that this approximation ignores the interaction of the carbon atoms with the Si—C substrate (used to form the graphene layer), which is assumed here to be weak.
Computed GNR bandstructures are shown in
There are also notable difference between CNTs and GNRs, however. Firstly, the two-fold degeneracy of the CNT states is removed—the lowest subband of the conduction and valence bands are nondegenerate in the GNR. Secondly, the lowest subband of the GNR has appreciably higher curvature than the corresponding CNT subband (for the semiconducting cases).
The most striking difference between the CNT and GNR bandstructures, however, is the much-smaller bandgap of the GNRs. This is illustrated in
The small bandgap of the GNR has important technological consequences, since it limits the band-to-band source-to-drain tunneling and ambipolar conduction (sufficiently short devices will be SD tunneling limited). As shown in
Transport in a perfect GNR (or CNT, for that matter) will be determined by phonon scattering, since vibrational distortions of the lattice cannot be removed at finite temperature. The continuum approach of computing phonon dispersion relations becomes invalid for narrow structures; the length scale for lateral variations in the displacement field must be many atomic distances in size. This is a condition that is clearly violated for a structure that is only a few atoms across. Thus, an atomistic approach is needed.
The semi-classical force-constant method is employed, which is essentially an application of Newton's Second Law, with a tensorial force-constant coupling each atom pair (see Background reference [65]). The total force on any given atom is obtained by summing the contributions of all neighbors within a given radius (fourth-nearest neighbors are included). A propagating wave form of the solution is then assumed in the transport direction (one-dimensional transport and k-vector for the GNR and CNT), which leads to a generalized Eigenvalue problem for the frequency, at any given wave vector. The problem is then solved for a set of wavevectors in the Brillouin zone, resulting in the complete dispersion relation (phonon bandstructure). Furthermore, the eigenvectors (multiplied by the wavevector-dependent phase factor) represent the atomic displacements of the various modes. The treatment of the CNT and GNR is virtually identical; all atoms experience a force coupling to all neighbors within a fourth-nearest neighbor radius. For the CNT, this means that periodic boundary conditions are applied. For the GNR, the edge atoms simply have fewer coupled neighbors. No displacement boundary conditions are applied; these arise naturally from the solution of the Eigen problem. The force constants are assumed not to change near the edge of the ribbon. This is an approximation, of course, but a reasonable one for a first-order calculation. More-detailed calculations would need to comprehend the influence of the substrate, as well as any other surrounding topography.
The resulting bandstructures for the GNR and CNT are shown in
Since the force-constant tensor does not couple in-plane displacements with out-of-plane forces (and vice versa), the in-plane and out-of-plane motions are decoupled. Thus, modes are either entirely in-plane, or entirely out-of-plane. For the GNR, this arises naturally. For the CNT, it is due to the neglect of curvature. The second two modes of the GNR and CNT are shown in
The key property that makes the CNT attractive for FET devices is its high mobility. While the GNR is qualitatively similar to the CNT, it is not necessarily clear that it will have similarly high mobility. The low-field phonon-limited mobility is computed for both the GNR and the CNT using the Born Scattering approach, similar to that outlined in Background references [67] and [68]. The overlap matrix elements are computed using direct integration of the previously computed electron and phonon wavefunctions. The selected rules are limited to forward momentum and conservation only (angular momentum would apply for the CNT as well, but not for the GNR). The overall mobility value is obtained using the Kubo-Greenwood formula.
The results of the mobility computation as a function of GNR and/or CNT size are summarized in
The mobility shown in
Whereas the vertical electric field has little influence on the bandstructure and mobility of GNRs and CNTs, the lateral field modulates it quite strongly. This is quantified using the Monte Carlo method, and the results are shown in
While the equal-size mobility of the GNR is higher than that of the CNT, it is perhaps more meaningful to compare the mobilities at equal bandgaps. The size of the bandgap determines the available range of voltages for a device operating in the ambipolar mode, as well as determines the ultimate limit for device scaling due to S/D tunneling. This comparison is illustrated in
GNRs vs. CNTs
Since many of the characteristics of CNTs stem from the underlying graphene lattice, the electrical characteristics of a CNT will be maintained even when the CNT is unrolled into the equivalent ribbon (which can be thought of as the planarized outer shell of the CNT) (see Background reference [16]). The softer edge boundary conditions on the ribbon, instead of more stringent periodic boundary conditions around the nanotube circumference, lower the graphene bandgap, but preserve its overall chiral properties (see Background reference [32]). A first-order analysis of graphene ribbons can follow almost the same methodology as that as CNTs. A two-dimensional (2D) graphene hexagonal lattice can be patterned into narrow ribbons that will create a quasi one-dimensional (1D) system with quantized states in the transversal direction. Two such 1D ribbons are shown in
The reader is cautioned to note that the nomenclature used in the literature for graphene nanoribbons (GNRs) is unfortunately exactly the opposite as for CNTs. For example, the GNR in
CNTs have been experimentally produced in the lab and their measured results have shown excellent characteristics for electronic applications (see Background reference [12]). The measured characteristics of CNTs include:
However, there are two major roadblocks in trying to use CNTs for any practical applications: Until now, there have been no credible solutions for arranging large numbers of CNTs on a substrate in order to integrate them into a circuit, and there have been no clear solutions for controlling their chirality during synthesis. Most of the experiments until now have consisted of the tedious manual selection of individual CNTs from a large number of synthesized CNTs with chiralities statistically distributed, followed by the manual arrangement of one or a small number of such CNTs in-situ (see Background references [5] and [51])). However, controlling the tubes chirality is an on-going effort, and the results until now have been unsatisfactory to the point where one can raise serious doubts that CNTs will ever be usable on a large scale as electronic devices.
This embodiment describes a direct relationship with work on CNTs and work on graphene done elsewhere. Between the two, the work on CNTs is much more mature. The work done on CNTs elsewhere includes:
The fabrication aspects of CNTs and GNRs is quite different, but all the other efforts, including device modeling and characterization, and including logic-circuit design, have many similarities and the present invention takes full advantage of those. The work on graphene done elsewhere includes:
In the present invention, graphene sheets are patterned into ribbons of given width and at given angle with respect to the two-dimensional hexagonal (honeycomb) lattice. Such GNRs have either metallic or semiconductor behavior depending on their general shape, specific dimensions, and orientation to the hexagonal graphene lattice.
The present invention discloses that GNRs can be used for building devices, wires, and circuits by patterning graphene using planar techniques in order to create metallic ribbons (wires and electrodes) and semiconductor ribbons (devices), of given width, angle, and shape, out of one template.
Being made out of a continuous graphene sheet such structures should exhibit no heptagon-pentagon Stone-Wales defects as in CNTs with junctions (see Background reference [49]). This means that the contact-channel interfaces are likely to be ohmic contacts rather than Schottky contacts. By using planar-patterning techniques, the alignment problem of nanotubes is implicitly solved. Likewise, the use of planar techniques also implicitly solves the chirality control problem. Since such GNRs have no top-dangling bonds, it means that such GNRs will allow high-k dielectric interfaces, similar to CNTs (see Background reference [32]), and thus will allow high mobility. From these considerations, it can be seen that GNRs have many of the strengths of nanotubes, minus many of their weaknesses.
In order to have useful devices, more than just metallic or semiconductor behavior is needed. Also needed is a way to gate the semiconductor ribbons in order to obtain switching and gain. The present invention gates graphene ribbons with metallic plates, or with another graphene ribbon orthogonal to the device. The lack of dangling bonds on the graphene surface enables high-k dielectric interfaces. Together with the long acoustic phonon-mean-free paths in graphene and their high thermal conductance (owing to the symmetry of their bands and their large C—C stiffness constants), this leads to ultra-high mobility of the gated graphene channel. While some of these properties exist for nanotubes, graphene devices are easier to scale in order to deliver a large drive current. This is in contrast with CNTs, which seem to suffer from fundamental alignment problems.
Additionally, GNRs can be used in graphene-ribbon circuits in which the devices are used by arranging them in a plane such that metallic and semiconductor alternate in order to create useful behavior. For example, two semiconductor GNRs in parallel can create an OR gate, and two GNRs in series can be used to create an AND gate.
Another important issue specific to GNRs (and not to CNTs) is the existence of dangling bonds at the ribbon edges. Depending on desired behavior, these edges can be kept active (see Background reference [32]) or passivated with other elements, such as H, carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, PbTe, or other oxides and materials known in the art used to chemically dope CNTs (see Background reference [11]). The way the edges are passivated can be an important feature of GNRs: By properly choosing elements (that could act like donors or acceptors) on the edges, it is possible to tune the electronic properties of the GNR, thus achieving more-interesting behaviors than those possible CNTs. An alternative to chemically doping the edges of GNRs is to electrostatically dope the GNR edges, a process that also has the benefit of being reversible.
Undoped GNR-based devices are intrinsically ambipolar; however, the desired NMOS- or PMOS-like asymmetric behavior can be obtained by shifting the Fermi level of the channel region by using metals with specific workfunctions for the gate or by doping chemically, electrostatically, or by other means.
Some sample GNR structures that are proposed by the present invention are shown in
This embodiment discloses a transistor based on graphene nanoribbons (GNRs), said switch having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a semiconducting GNR disposed on said substrate having a variable resistance electrically connected between said source GNR and said drain GNR, wherein said semiconducting GNR is disposed between said source GNR and said drain GNR, and wherein said semiconducting GNR edges are armchair-type; and a conductive gate GNR disposed on said substrate proximal and orthogonal to said semiconducting GNR, for controlling said resistance thereof, wherein said gate GNR is substantially metallic, wherein said gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said gate GNR and said source GNR, wherein a second gap exists between said gate GNR and said drain GNR, and wherein said semiconducting GNR spans said first and second gaps.
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment discloses a NOT gate based on graphene nanoribbons (GNRs), said gate having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a semiconducting GNR disposed on said substrate electrically connected between said source GNR and said drain GNR, wherein said semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said semiconducting GNR has armchair edging, and wherein said semiconducting GNR is physically disposed in series at an angle of zero degrees relative to said source GNR and said drain GNR; and a conductive gate GNR disposed on said substrate proximal and orthogonal to said semiconducting GNR, for controlling said semiconducting GNR resistance thereof, wherein said gate GNR is substantially metallic, wherein said gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said gate GNR and said source GNR, wherein a second gap exists between said gate GNR and said drain GNR, wherein said semiconducting GNR spans said first and second gaps, and wherein when said semiconducting GNR turns OFF when a gate signal is applied, and turns ON when a gate signal is not applied.
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment discloses a parallel-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two parallel GNR-based transistors, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said drain GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said drain GNR; a second semiconducting GNR disposed on said substrate and electrically connected between the source and the drain, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said source GNR and said drain GNR; a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said drain GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in parallel with each other
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment can be further extended by adding one or more parallel transistors to the parallel-transistor network substrate in the same basic manner as was done for the first two parallel transistors described.
This embodiment discloses a series-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two GNR-based transistors in series with each other, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive intermediary drain/source GNR disposed on a substrate, wherein said intermediary drain/source GNR is substantially metallic, and wherein said intermediary drain/source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said intermediary drain/source GNR; a second semiconducting GNR disposed on said substrate and electrically connected between said intermediary drain/source GNR and said drain GNR, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said intermediary drain/source GNR and said drain GNR; a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, and wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, and wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said intermediary drain/source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in series with each other.
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment can be further extended by adding one or more series transistors to the parallel-transistor network substrate in the same basic manner as was done for the first two series transistors described. This will obviously require the use of additional intermediary drain/source GNRs in addition to the new transistors.
This embodiment discloses a capacitor device based on graphene nanoribbons (GNRs), said capacitor having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a first conductive surface GNR disposed on a substrate, wherein said first surface GNR is substantially metallic, wherein said first surface GNR edges are zigzag-type, jagged-type, or armchair-type, and wherein said first surface GNR is electrically connected to a first conductive GNR or graphene nanowire; a second conductive surface GNR disposed on a substrate, wherein said second surface GNR is substantially metallic, wherein said second surface GNR edges are zigzag-type, jagged-type, or armchair-type, and wherein said second surface GNR is electrically connected to a second conductive GNR or graphene nanowire; wherein said first and second surface GNRs are proximal with each other, but separated by a gap containing a dielectric material.
This embodiment discloses an integrated circuit substantially based on graphene nanoribbons (GNRs), said integrated circuit comprising of any combination of transistors, NOT gates, OR gates, AND gates, and capacitors defined by the embodiments describing those devices above, respectively.
This embodiment discloses a method for making a transistor based on graphene nanoribbons (GNRs), said switch having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising the steps of: providing a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; providing a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; providing a semiconducting GNR disposed on said substrate having a variable resistance electrically connected between said source GNR and said drain GNR, wherein said semiconducting GNR is disposed between said source GNR and said drain GNR, and wherein said semiconducting GNR edges are armchair-type; and providing a conductive gate GNR disposed on said substrate proximal and orthogonal to said semiconducting GNR, for controlling said resistance thereof, wherein said gate GNR is substantially metallic, wherein said gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said gate GNR and said source GNR, wherein a second gap exists between said gate GNR and said drain GNR, and wherein said semiconducting GNR spans said first and second gaps.
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment discloses a method for making an integrated circuit substantially based on graphene nanoribbons (GNRs), said method comprising the steps of providing any combination of transistors, NOT gates, OR gates, AND gates, and capacitors defined by the embodiments describing those devices above, respectively.
This embodiment discloses a computing system, said computing system having at least one microprocessor, said at least one microprocessor having transistors, NOT gates, OR gates, AND gates, and capacitors, wherein said computing system further comprises at least one transistor, NOT gate, OR gate, AND gate, or capacitor defined by the embodiments describing those devices above, respectively.
This embodiment discloses a computer program, said computing program executed by a computing system, said computing system having at least one microprocessor, said at least one microprocessor having transistors, NOT gates, OR gates, AND gates, and capacitors, wherein at least one transistor, NOT gate, OR gate, AND gate, or capacitor used in the execution of said computer program is defined by the embodiments describing those devices above, respectively.
This embodiment discloses a method for performing a NOT calculation using a NOT gate based on graphene nanoribbons (GNRs); said gate having a substrate, said graphene originating from a continuous graphene sheet; said GNRs derived from said sheet using planar techniques; said gate having a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; said gate having a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; said gate having a semiconducting GNR disposed on said substrate electrically connected between said source GNR and said drain GNR, wherein said semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said semiconducting GNR has armchair edging, and wherein said semiconducting GNR is physically disposed in series at an angle of zero degrees relative to said source GNR and said drain GNR; and said gate having a conductive gate GNR disposed on said substrate proximal and orthogonal to said semiconducting GNR, for controlling said semiconducting GNR resistance thereof, wherein said gate GNR is substantially metallic, wherein said gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said gate GNR and said source GNR, wherein a second gap exists between said gate GNR and said drain GNR, wherein said semiconducting GNR spans said first and second gaps, and wherein when said semiconducting GNR turns OFF when a gate signal is applied, and turns ON when a gate signal is not applied; said method comprising the steps of: making a power source available at said source GNR; applying a logical voltage signal to said gate GNR, wherein said logical signal is selected from the group consisting of “1” or “0”, wherein said logical voltage signal and its associated current path is configured to desaturate said semiconductor GNR if a logical “1” signal is applied, and wherein said logical voltage signal and its associated current path is configured to saturate said semiconductor GNR if a logical “0” signal is applied; and if said semiconductor GNR is saturated, then making said power source available to said drain GNR.
This embodiment discloses a method for performing an OR calculation using at least one parallel-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two parallel GNR-based transistors, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said drain GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said drain GNR; a second semiconducting GNR disposed on said substrate and electrically connected between the source and the drain, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said source GNR and said drain GNR; a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said drain GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in parallel with each other, said method comprising the steps of: making a power source available at said source GNR; applying a logical voltage signal to at least one of said first gate GNR or said second gate GNR, wherein said logical signal to said first gate GNR is selected from the group consisting of “1” or “0”, wherein said logical signal to said second gate GNR is selected from the group consisting of “1” or “0”, wherein said logical voltage signal to said first gate GNR and its associated current path is configured to saturate said first semiconductor GNR if a logical “1” signal is applied, wherein said logical voltage signal to said first gate GNR and its associated current path is configured to desaturate said first semiconductor GNR if a logical “0” signal is applied, wherein said logical voltage signal to said second gate GNR and its associated current path is configured to saturate said second semiconductor GNR if a logical “1” signal is applied, wherein said logical voltage signal to said second gate GNR and its associated current path is configured to desaturate said second semiconductor GNR if a logical “0” signal is applied; and if either said first semiconductor GNR is saturated or said second semiconductor GNR is saturated, then making said power source available to said drain GNR.
This embodiment discloses a method for performing an AND calculation using a at least one series-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two GNR-based transistors in series with each other, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, comprising: a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive intermediary drain/source GNR disposed on a substrate, wherein said intermediary drain/source GNR is substantially metallic, and wherein said intermediary drain/source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said intermediary drain/source GNR; a second semiconducting GNR disposed on said substrate and electrically connected between said intermediary drain/source GNR and said drain GNR, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said intermediary drain/source GNR and said drain GNR; a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, and wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, and wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said intermediary drain/source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in series with each other, said method comprising the steps of: making a power source available at said source GNR; applying a logical voltage signal to at least one of said first gate GNR or said second gate GNR, wherein said logical signal to said first gate GNR is selected from the group consisting of “1” or “0”, wherein said logical signal to said second gate GNR is selected from the group consisting of “1” or “0”, wherein said logical voltage signal to said first gate GNR and its associated current path is configured to saturate said first semiconductor GNR if a logical “1” signal is applied, wherein said logical voltage signal to said first gate GNR and its associated current path is configured to desaturate said first semiconductor GNR if a logical “0” signal is applied, wherein said logical voltage signal to said second gate GNR and its associated current path is configured to saturate said second semiconductor GNR if a logical “1” signal is applied, wherein said logical voltage signal to said second gate GNR and its associated current path is configured to desaturate said second semiconductor GNR if a logical “0” signal is applied; if said first semiconductor GNR is saturated, then making said power source available to said intermediary drain/source GNR; and if said second semiconductor GNR is saturated, then making any said power source that is available on said intermediary drain/source GNR available to said drain GNR.
This embodiment discloses a method for making a parallel-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two parallel GNR-based transistors, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, said method comprising the steps of: providing a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; providing a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; providing a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said drain GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said drain GNR; providing a second semiconducting GNR disposed on said substrate and electrically connected between the source and the drain, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said source GNR and said drain GNR; providing a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said drain GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; providing a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in parallel with each other
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment can be further extended by adding one or more parallel transistors to the parallel-transistor network substrate in the same basic manner as was done for the first two parallel transistors described.
This embodiment discloses a method for making a series-transistor network, said network based on graphene nanoribbons (GNRs), said network having at least two GNR-based transistors in series with each other, said network having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, said method comprising the steps of: providing a conductive source GNR disposed on a substrate, wherein said source GNR is substantially metallic, and wherein said source GNR edges are zigzag-type, jagged-type, or armchair-type; a conductive intermediary drain/source GNR disposed on a substrate, wherein said intermediary drain/source GNR is substantially metallic, and wherein said intermediary drain/source GNR edges are zigzag-type, jagged-type, or armchair-type; providing a conductive drain GNR disposed on said substrate and spaced apart from the source, wherein said drain GNR is substantially metallic, and wherein said drain GNR edges are zigzag-type, jagged-type, or armchair-type; providing a first semiconducting GNR disposed on said substrate and electrically connected between said source GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said first semiconducting GNR has armchair edging, and wherein said first semiconducting GNR is physically disposed between said source GNR and said intermediary drain/source GNR; providing a second semiconducting GNR disposed on said substrate and electrically connected between said intermediary drain/source GNR and said drain GNR, wherein said second semiconducting GNR has two operational states, the first state being ON and the second state being OFF, wherein said second semiconducting GNR has armchair edging, and wherein said second semiconducting GNR is physically disposed between said intermediary drain/source GNR and said drain GNR; providing a first conductive gate GNR disposed on said substrate proximal and orthogonal to said first semiconducting GNR, for controlling said first semiconducting GNR resistance thereof, wherein said first gate GNR is substantially metallic, and wherein said first gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a first gap exists between said first gate GNR and said source GNR, wherein a second gap exists between said first gate GNR and said intermediary drain/source GNR, wherein said first semiconducting GNR spans said first and second gaps, and wherein when said first gate GNR changes the conducting state of said first semiconducting GNR between ON and OFF based on an applied signal by way of said first gate GNR; providing a second conductive gate GNR disposed on said substrate proximal and orthogonal to said second semiconducting GNR, for controlling said second semiconducting GNR resistance thereof, wherein said second gate GNR is substantially metallic, and wherein said second gate GNR edges are zigzag-type, jagged-type, or armchair-type, wherein a third gap exists between said second gate GNR and said intermediary drain/source GNR, wherein a fourth gap exists between said second gate GNR and said drain GNR, wherein said second semiconducting GNR spans said third and fourth gaps, and wherein when said second gate GNR changes the conducting state of said second semiconducting GNR between ON and OFF based on an applied signal by way of said second gate GNR; wherein the power-output-current paths for said first and second semiconducting GNRs are electrically connected in series with each other.
This embodiment can be further extended wherein said semiconducting GNR is passivated with an element selected from the group consisting of carbon, silicon, germanium, grey tin, SiGe, SiC, AlAs, AlP, AlSb, BN, BP, GaAs, GaN, GaSb, H, InAs, InP, InSb, CdS, CdSe, CdTe, ZnO, ZnS, PbS, and PbTe.
This embodiment can be further extended wherein said semiconducting GNR is passivated with a semiconducting material that is n-type or is p-type.
This embodiment can be further extended wherein the edges of said semiconducting GNR are doped to form a doping profile, wherein said doping profile is selected from the group consisting of NPN, PNP, PIP, NIN, and PIN.
This embodiment can be further extended wherein said doping is accomplished by chemical-doping means or by electrostatic-doping.
This embodiment can be further extended by adding one or more series transistors to the parallel-transistor network substrate in the same basic manner as was done for the first two series transistors described. This will obviously require the use of additional intermediary drain/source GNRs in addition to the new transistors.
This embodiment discloses a method for making a capacitor device based on graphene nanoribbons (GNRs), said capacitor having a substrate, said graphene originating from a continuous graphene sheet, said GNRs derived from said sheet using planar techniques, said method comprising the steps of: providing a first conductive surface GNR disposed on a substrate, wherein said first surface GNR is substantially metallic, wherein said first surface GNR edges are zigzag-type, jagged-type, or armchair-type, and wherein said first surface GNR is electrically connected to a first conductive GNR or graphene nanowire; providing a second conductive surface GNR disposed on a substrate, wherein said second surface GNR is substantially metallic, wherein said second surface GNR edges are zigzag-type, jagged-type, or armchair-type, and wherein said second surface GNR is electrically connected to a second conductive GNR or graphene nanowire; wherein said first and second surface GNRs are proximal with each other, but separated by a gap containing a dielectric material.
Overall, the various embodiments of the present invention generally provides monolithically integrated graphene nanoribbon (GNR) devices, interconnect, and circuits that overcome most of the difficulties with carbon nano-tube (CNT) devices and circuits, by having implicit control over the chirality, being self-aligned, and having no interface mismatch between the device and interconnect regions.
The various embodiments of the present invention may be utilized and/or combined for a number of products and services, such as, but not limited to, devices and circuits that could potentially revolutionize the semiconductor industry. Many groups of researchers are pursuing ideas that could either allow further scaling (“More Moore”), or find a worthy alternative to CMOS (“Beyond Moore”). GNRs, like CNTs, fall mostly in the “More Moore” category, but with extremely attractive characteristics. The various embodiments of the present invention offers, among other things, an alternative to CNTs by providing distinct advantages over CNTs, as GNRs do not require difficult arrangement of the devices, can offer superior chirality control, and have perfect interfaces between devices and interconnects, with no defects. Moreover, as compared to CMOS, the graphene structures described herein scale to very small dimensions, and offer superior electronic properties (faster operation at lower power consumption).
Notwithstanding, those skilled in the art will have no difficulty devising myriad obvious variations and improvements to the present invention, all of which are intended to be encompassed within the scope of the claims which follow.
This application claims priority from U.S. application No. 60/997,056, filed Oct. 1, 2007, which application is incorporated herein by references for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 60997056 | Oct 2007 | US |
