Patent Application
20110049563
1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a MOS-gate power semiconductor device.
2. Description of the Related Art
Semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a metal-oxide semiconductor field effect transistor (MOSFET) are mainly used as switching devices in the field of power electronic applications. That is, the semiconductor devices are used as semiconductor switching devices in the power electronic applications such as an H-bridge inverter, a half-bridge inverter, a 3-phase inverter, a multi-level inverter, and a converter.
However, in power electronic circuits including the semiconductor switching devices (that is, semiconductor devices used as the semiconductor switching devices), the semiconductor switching devices may happen to be deteriorated or destructed by the overcurrent flow due to a malfunction of driving circuitry. Accordingly, it is necessary to avoid such failures due to the overcurrent and moreover to prevent the deterioration and/or destruction of the semiconductor switching devices.
Hereinafter, operations of an H-bridge inverter circuit employing the semiconductor switching devices will be described along with a shoot-through phenomenon as an example of the failure in the circuit.
As shown in
The semiconductor switching devices M1 to M4 included in the H-bridge inverter circuit are alternately turned on and off in a switching sequence to supply AC power to the load 120 connected to the output node 110 between the semiconductor switching devices. Here, each pair of semiconductor switching devices is called arm or leg.
When the semiconductor switching devices M1 and M3 are turned on and the semiconductor switching devices M2 and M4 are turned off under the control of a driving circuit for the semiconductor switching devices, a current flows in the direction of A. On the contrary, when the semiconductor switching devices M2 and M4 are turned on and the semiconductor switching devices M1 and M3 are turned off, the current flows in the direction of B.
Accordingly, as shown in
Therefore, it is indispensible to control the semiconductor switching devices M1 and M4 (or M2 and M3) disposed in the same arm not to simultaneously be in the ON state. As shown in
Otherwise, a short circuit is formed between the semiconductor switching devices disposed in the same arm to cause the shoot-through phenomenon, when the semiconductor switching devices disposed in the same arm are simultaneously in the ON state. That is, a very large short circuit current flows through the formed short circuit, which causes the deterioration and/or destruction of the semiconductor switching devices.
Referring to
Referring to
When the semiconductor device shown in
In an abnormal state such as the above-mentioned shoot-through phenomenon, an overcurrent flows to the outside via the emitter metal electrode 345, which can cause the deterioration and/or destruction of the semiconductor switching device.
To prevent the shoot-through phenomenon, the semiconductor devices are controlled with the dead time. However, the possibility that the shoot-through phenomenon occurs cannot be completely excluded in various abnormal states where the control sequence of the driving circuit is not normally designed or the driving circuit for the semiconductor switching devices operates erroneously.
Particularly, since a tail current exists due to the characteristic of the IGBT, a sufficient dead time is required for preventing the shoot-through phenomenon. However, the elongation of the dead time causes an increase in harmonics due to the distortion in output waveform of an inverter, thereby lowering the performance of the inverter.
Therefore, there is a need for preventing the deterioration and/or destruction of a semiconductor switching device by switching or maintaining its operating state to or in the OFF state in an abnormal state such as the shoot-through phenomenon, and suppressing a failure from occurring in the driving circuit.
The above-mentioned background art is technical information thought out to make the invention or learned in the course of making the invention by the inventor, and cannot be thus said to be technical information known to the public before filing the invention.
An advantage of some aspects of the invention is that it provides a MOS-gate power semiconductor device which can prevent deterioration and/or destruction of a semiconductor switching device by switching or maintaining its operating state to or in the OFF state in an abnormal state such as a shoot-through phenomenon and suppress a failure from occurring in a driving circuit.
Another advantage of some aspects of the invention is that it provides a MOS-gate power semiconductor device which can fundamentally suppress a shoot-through phenomenon from occurring in an inverter circuit or the like.
Another advantage of some aspects of the invention is that it provides a MOS-gate power semiconductor device which can allow a decrease in weight, thickness, and size of a power electronic circuit by building a self protecting function in the semiconductor switching device without being embodied in combination with a particular diode.
Other advantages of the invention will be easily understood from the following description.
According to an aspect of the invention, there is provided a MOS-gate power semiconductor device including: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line.
The P-type wells may serve as an anode of a diode and the N-type wells may serve as a cathode of the diode.
The P-type wells and the N-type wells may be formed by performing an ion implantation process and a diffusion process on a semiconductor substrate.
In the MOS-gate power semiconductor device, a plurality of diodes formed using P-type ions of the P-type wells and N-type ions of the N-type wells may be arranged in one or more of a serial connection and a parallel connection between a gate terminal and an emitter terminal.
The MOS-gate power semiconductor device may serve as one or more of an insulated gate bipolar transistor (IGBT) and a metal-oxide semiconductor field effect transistor (MOSFET).
According to another aspect of the invention, there is provided a MOS-gate power semiconductor device including: one or more P-type wells formed in a semiconductor substrate so as to electrically be connected to an anode metal pad exposed from a surface of the MOS-gate power semiconductor device; and one or more N-type wells formed in the semiconductor substrate so as to electrically be connected to a cathode metal pad exposed from the surface.
The anode metal pad may be electrically connected to an emitter metal electrode and the cathode metal pad may be electrically connected to one or more of a gate metal electrode and a gate bus line.
The P-type wells and the N-type wells may be formed by performing an ion implantation process and a diffusion process on the semiconductor substrate.
The N-type wells may be formed in the P-type wells so as to serve as a PN-junction diode.
The P-type wells and the N-type wells may be formed in an area other than an edge termination area.
In the MOS-gate power semiconductor device, the anode metal pad and the cathode metal pad may be formed in an active area so as to be exposed from the active area.
In the MOS-gate power semiconductor device, a plurality of diodes are arranged in one or more of a serial connection and a parallel connection between a gate metal terminal and an emitter metal terminal by wiring the anode metal pad and the cathode metal pad.
The MOS-gate power semiconductor device may serve as one or more of an insulated gate bipolar transistor (IGBT) and a metal-oxide semiconductor field effect transistor (MOSFET).
According to the aspects of the invention, it is possible to prevent deterioration and/or destruction of a semiconductor switching device by switching or maintaining its operating state to or in the OFF state in an abnormal state such as a shoot-through phenomenon and to suppress a failure from occurring in a driving circuit.
It is also possible to fundamentally suppress a shoot-through phenomenon from occurring in an inverter circuit or the like.
It is also possible to allow a decrease in weight, thickness, and size of power electronic circuit by building a self protecting function in the semiconductor switching device without being embodied in combination with a particular diode.
The invention can be variously modified in various forms and specific embodiments will be described and shown in the drawings. However, the embodiments are not intended to limit the invention, but it should be understood that the invention includes all the modifications, equivalents, and replacements belonging to the spirit and the technical scope of the invention. When it is determined that detailed description of known techniques associated with the invention makes the gist of the invention obscure, the detailed description will be omitted.
Terms such as “first” and “second” can be used to describe various elements, but the elements are not limited to the terms. The terms are used only to distinguish one element from another element.
The terms used in the following description are used to merely describe specific embodiments, but are not intended to limit the invention. An expression of the singular number includes an expression of the plural number, so long as it is clearly read differently. The terms such as “include” and “have” are intended to indicate that features, numbers, steps, operations, elements, components, or combinations thereof used in the following description exist and it should be thus understood that the possibility of existence or addition of one or more different features, numbers, steps, operations, elements, components, or combinations thereof is not excluded.
If it is mentioned that an element such as a layer, a region, and a substrate is disposed “on” another element or extends “onto” another element, it should be understood that the element is disposed directly on another element or extends directly onto another element, or still another element is interposed therebetween. On the contrary, if it is mentioned that an element is disposed “directly on” another element or extends “directly onto” another element, it should be understood that still another element is not interposed therebetween. If it is mentioned that an element is “connected to” or “coupled to” another element, it should be understood that still another element may be interposed therebetween, as well as that the element may be connected or coupled directly to another element. On the contrary, if it is mentioned that an element is “connected directly to” or “coupled directly to” another element, it should be understood that still another element is not interposed therebetween.
Relative terms such as “below”, “above”, “upper”, “lower”, “horizontal”, “lateral”, and “vertical” can be used to describe the relative relation of an element, layer, or region to another element, layer, or region as shown in the drawings. The terms are intended to include another direction of a device relative to an orientation shown in the drawings.
The exemplary embodiments of the invention will be described now in detail with reference to the accompanying drawings. Although an IGBT used as a semiconductor switching device in an H-bridge inverter circuit will be mainly described, a semiconductor switching device with the same technical spirit can be applied to various power electronics fields such as a half-bridge inverter, a 3-phase inverter, a multi-level inverter, and a converter without any particular restriction.
As shown in
An output node 110 supplying current to a load 120 is disposed between the upper semiconductor switching device M1 and the lower semiconductor switching device M4.
A diode 420 is interposed between the output node 110 and a connection node 410. The connection node 410 is connected to the gate terminal of the upper semiconductor switching device M1 via a conductive line 430. Accordingly, the diode 420 is disposed between the emitter terminal and the gate terminal of the upper semiconductor switching device M1 and between the emitter terminal of the upper semiconductor switching device M1 and the collector terminal of the lower semiconductor switching device M4. When the upper semiconductor switching device M1 and the lower semiconductor switching device M4 is a power MOSFET, the diode 420 is disposed between the source terminal and the gate terminal of the upper semiconductor switching device M1 and between the source terminal of the upper semiconductor switching device M1 and the drain terminal of the lower semiconductor switching device M4.
The diode 420 serves to turn off the upper semiconductor switching device M1 or to maintain the upper semiconductor switching device M1 in the OFF state, when a current is input to the lower semiconductor switching device M4. As described with reference to
For example, in an abnormal state of the circuit where two semiconductor switching devices disposed in one arm are simultaneously turned on, the gate potential of the upper semiconductor switching device M1 is lower than the emitter potential due to the voltage drop (about 0.7 V) due to the turning-on of the diode 420. Accordingly, the gate potential of the upper semiconductor switching device M1 is not maintained to be equal to or greater than a threshold voltage and the upper semiconductor switching device M1 is forcibly turned off, thereby preventing the shoot-through phenomenon.
It is preferable that the breakdown voltage of the diode is set to be equal to or greater than the gate oxide breakdown voltage of the semiconductor switching device and the forward voltage drop at the time of turning on the diode is small.
Referring to
An N-type well 510 for forming a PN-junction diode is formed in the P-type well 320 formed in the N-type semiconductor substrate 315. The gate oxide film 330 is formed on the P-type well 320 and the N-type well 510. A gate poly pad 365 is formed on the gate oxide film 330. The gate poly pad 365 is electrically connected to the gate pad electrode formed of metal. The gate poly pad 365 may not be formed as needed, and the thickness of the gate oxide film can be changed variously.
As shown in
The P-type wells serving as the anodes are electrically connected to the emitter metal electrode 345 directly or indirectly. The N-type wells serving as the cathodes are electrically connected to the gate metal electrode 210 directly or indirectly. For example, the P-type wells are electrically connected to the emitter metal electrode 345 via a contact hole and the N-type wells are electrically connected to the gate pad electrode 210 via a contact hole.
The layout of the semiconductor switching device 60 having the above-mentioned configuration is conceptually shown in
When the semiconductor switching device 600 shown in
Accordingly, in a normal state, the upper semiconductor switching device M1 supplies a current to the load 120 via the emitter metal electrode 345. However, in an abnormal state, when the upper semiconductor switching device M1 and the lower semiconductor switching device M4 are both turned on and a shoot-through phenomenon may occur, the current flowing out from the emitter metal electrode 345 flows to the gate metal electrode 210 via the diode 420. In this case, a voltage drop is caused by the diode 420 and the gate potential is lower than the emitter potential. Accordingly, the gate potential of the upper semiconductor switching device M1 is less than a threshold voltage and thus the upper semiconductor switching device M1 is forcibly turned off. Since the upper semiconductor switching device M1 is turned off it is possible to prevent the deterioration and/or destruction of the upper semiconductor device M1 and thus to prevent the shoot-through phenomenon from occurring.
The anode and the cathode of a diode built in a semiconductor device 700 may include a metal electrode allowing the wire bonding for electrical connection between the emitter metal electrode 345 and the gate metal electrode 210.
Referring to
The P-type wells and the N-type wells formed under than active area 220 so as to serve as a PN-junction diode are formed as described above so that the N-type wells are included in the P-type wells. The P-type wells are electrically connected to the anode pad 720 and the N-type wells are electrically connected to the cathode pad 710.
The cathode pad 710 is electrically connected to the gate metal electrode 210 of the semiconductor device 700 using a metal wire and the anode pad 720 is electrically connected to the emitter metal electrode 345 of the semiconductor device 700 using a metal wire. Here, when the semiconductor device is a MOSFET, the emitter corresponds to the source.
While the invention is described with reference to the embodiments, it will be understood by those skilled in the art that the invention is modified and changed in various forms without departing from the spirit and scope of the invention described in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2009-0082820 | Sep 2009 | KR | national |
