BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view explanatory of the length of current paths between a sidewall and an impurity layer in a conventional MOS transistor 500;
FIG. 2 is a cross-sectional view showing one of steps of manufacturing a MOS transistor 100 according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 6 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 7 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 8 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 9 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 10 is a cross-sectional view showing one of the steps of manufacturing the MOS transistor 100 according to the first embodiment of the present invention;
FIG. 11 is a cross-sectional view explanatory of the length of current paths between a sidewall 7 and an impurity layer 24 in the MOS transistor 100;
FIG. 12 is a cross-sectional view showing one of steps of manufacturing a MOS transistor 200 according to a second embodiment of the present invention;
FIG. 13 is a view explanatory of a lithography mask pattern of a semiconductor device suitable for application of the MOS transistor 100 or 200;
FIG. 14 is a view explanatory of a lithography mask pattern of a semiconductor device suitable for application of the MOS transistor 100 or 200;
FIG. 15 is a cross-sectional view explanatory of a structure of a MOS transistor 300 according to a third embodiment of the present invention; and
FIG. 16 is a view explanatory of a lithography mask pattern of a semiconductor device suitable for application of the MOS transistor 300.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In a MOS transistor having a structure in which silicon of a source and a drain is raised on a substrate by using selective epitaxial growth technique, an exemplary aspect of the present invention is focused on the fact that the high resistance of the raised silicon inhibits an on-state current Ion of the transistor. Accordingly, a portion of the raised silicon is removed. As a result, the parasitic resistance of the source and the drain can be reduced, and an on-state current Ion can be improved.
A manufacturing method of a MOS transistor 100 according to a first exemplary embodiment of the present invention will be described below with reference to FIGS. 2 to 11. FIGS. 2 to 10 are cross-sectional views showing a series of steps of manufacturing a MOS transistor 100. Each of FIGS. 2 to 10 includes reference numerals necessary for explanation of each step.
As shown in FIG. 2, a gate 9 is formed on a silicon substrate 1 by a general process. The gate 9 includes a gate insulation film 2, a gate polysilicon 3, a tungsten nitride 4, a tungsten gate electrode 5, an offset insulation film 6, and sidewalls 7 and 8. A source 10 and a drain 11 are formed on the silicon substrate 1 at the left and right sides of the gate 9, respectively. Silicon oxide films 12 and 13 are formed on the left and right sides of the silicon substrate 1, respectively.
Then, as shown in FIG. 3, the source 10 and the drain 11 of the silicon substrate 1 are raised by a selective epitaxial growth technique to thereby form a structure of a MOS transistor. A silicon layer 14 is formed on the source 10, and a silicon layer 15 is formed on the drain 11.
Next, as shown in FIG. 4, an impurity having a high concentration is introduced into upper surfaces of the silicon layers 14 and 15 by an ion implantation method so as to form impurity layers 16 and 17.
Subsequently, as shown in FIG. 5, a silicon nitride film 18 is grown on the overall surface of the substrate.
Then, as shown in FIG. 6, the silicon nitride film 18 is etched back so that silicon nitride films 19, 20, and 21 are left on the substrate after the etch-back. The silicon nitride film 19 is formed so as to surround the gate 9. The silicon nitride film 20 is formed on leftward ends of the silicon layer 14 and the impurity layer 16. The silicon nitride film 21 is formed on rightward ends of the silicon layer 15 and the impurity layer 17.
Next, while the silicon nitride films 19 and 20 are used as a mask, the silicon layer 14 and the impurity layer 16 are etched so as to form a recessed portion 22 as shown in FIG. 7. Similarly, while the silicon nitride films 19 and 21 are used as a mask, the silicon layer 15 and the impurity layer 17 are etched so as to form a recessed portion 23. It is desirable that the length of a horizontal line connecting between a lower end of the sidewall 7 and the recessed portion 22 is equal to or longer than the thickness of the silicon layer 14. Similarly, it is desirable that the length of a horizontal line connecting between a lower end of the sidewall 8 and the recessed portion 23 is equal to or longer than the thickness of the silicon layer 15.
Subsequently, as shown in FIG. 8, an impurity having a high concentration is introduced into the recessed portions 22 and 23 by an ion implantation method so as to form impurity layers 24 and 25. This process may be omitted when the silicon layers 14 and 15 have a sufficiently low resistance. Furthermore, after contact holes, which will be described later, are formed, an impurity may be introduced into only bottoms of the contact holes by an ion implantation method so as to form an impurity layer on a portion of the recessed portion 22 and form an impurity layer on a portion of the recessed portion 23. Then a heat treatment is performed to activate the impurity in the impurity layers 24 and 25 as needed.
Then, as shown in FIG. 9, an interlayer dielectric 26 is formed by a general process.
Next, as shown in FIG. 10, contact holes 27 and 28 are formed in the interlayer dielectric 26 by a general process. Contacts 29 and 30 are formed within the contact holes 27 and 28, respectively. Metal interconnection layers 31 and 32 are formed on the interlayer dielectric 26. Specifically, an impurity is introduced into the contact holes 27 and 28 by an ion implantation method. A silicide layer is formed within the contact holes 27 and 28 by a general semiconductor fabrication process. Polysilicon including a doped impurity may be used as a material to be filled in the contact holes. Furthermore, the same effects can be attained even if no silicide is formed on interfaces between the polysilicon and the silicon layers 14 and 15 formed by selective epitaxial growth.
The present embodiment provides a MOS transistor having the following structure. A portion of the silicon layers 14 and 15 formed by selective epitaxial growth is removed so as to form inclination portions inclined downward in directions away from the sidewalls 7 and 8. The impurity layers 24 and 25 are formed on the inclination portions. Since the portion of the silicon layers 14 and 15, which have a high resistance, is removed, the parasitic resistance of the source and the drain is reduced in the MOS transistor. As a result, an on-state current Ion of the MOS transistor can be increased. Referring to FIG. 11, two arrows, i.e., current paths 33 and 34 extend from a lower end portion of the sidewall 7 toward the impurity layer 24 on the recessed portion 22. It can be seen that those current paths 33 and 34 have substantially the same length. In a group of lines extending radially from the lower end portion of the sidewall 7 toward the impurity layer 24, all of lines located between the current paths 33 and 34 are shorter than the current paths 33 and 34.
Next, a manufacturing method of a MOS transistor 200 according to a second exemplary embodiment of the present invention will be described.
The explanation of the first embodiment with reference to FIGS. 2 to 7 can also be applied to the second embodiment and is omitted herein.
In the first embodiment, after the recessed portions 22 and 23 are formed as shown in FIG. 7, the impurity layers 24 and 25 are formed on the recessed portions 22 and 23. In the second embodiment, as shown in FIG. 12, metal or semiconductor is introduced onto the recessed portions 22 and 23 so as to form low-resistance layers 35 and 36 in a self-aligned manner. For example, cobalt and nickel are used as the metal to be introduced. However, any metals capable of forming a silicide layer can be used as the metal to be introduced. Furthermore, germanium may be introduced so as to form a silicon germanide layer.
Although the present invention has been described based on the preferred exemplary embodiments, it is not limited to the illustrated embodiments. It would be apparent to those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the present invention.
For example, the MOS transistors 100 and 200 described in the first and second embodiments are used in a portion of a semiconductor device shown in FIG. 13 or 14. FIGS. 2 to 12 correspond to a cross-sectional view taken along line A-A′ of FIG. 13 or 14. More specifically, for example, the MOS transistors 100 and 200 can be applied to a contact portion of a storage node in a DRAM. Furthermore, the MOS transistors 100 and 200 can be applied to a peripheral circuit of a DRAM.
FIGS. 2 to 12 illustrate a MOS transistor having one gate located between two recessed portions. However, the present invention is not limited to the illustrated examples. For example, it would be apparent to those skilled in the art that the present invention can be applied to a MOS transistor having two gates located between two recessed portions as shown in FIGS. 15 and 16. FIG. 15 is a cross-sectional view taken along line B-B′ of a MOS transistor produced by a lithography mask pattern as shown in FIG. 16. Such a MOS transistor can be used in a pass gate portion of a DRAM having 6F2 layout.
Furthermore, it would be apparent to those skilled in the art that the present invention can be applied to a PMOS transistor and an NMOS transistor in a CMOS device.
In a case where the silicon layer has a high resistance to some extent, it is desirable that a conductive layer be provided along the inclination portion. Conversely, in a case where the silicon layer has a low resistance, such a conductive layer may not necessarily be provided.
For example, the inclination portion may be formed as a portion of a recessed portion.
It is desirable that the MOS transistor include a contact hole having a bottom formed by at least a portion of the inclination portion on the silicon layer. At that time, in a case where the silicon layer has a high resistance to some extent, it is desirable that a conductive layer be provided on the bottom of the contact hole.
Examples of the conductive layer include an impurity layer introduced by an ion implantation method and a conductive layer formed in a self-aligned manner by metal or semiconductor and the silicon layer. For example, cobalt and nickel are used as the metal. However, any metals capable of forming a silicide layer can be used as the metal. Furthermore, germanium may be used as the semiconductor. In this case, the conductive layer is a silicon germanide layer.
Examples of the contact in the contact hole include a silicide layer formed by introducing an impurity into the contact hole by an ion implantation method and polysilicon including a doped impurity.
Furthermore, an exemplary aspect of the present invention provides a semiconductor device in which the aforementioned MOS transistors are connected to each other. The semiconductor device includes a recessed portion located between two of the gates of the MOS transistors. The recessed portion is formed by connecting the inclination portions of the MOS transistors to each other. The semiconductor device also includes a contact hole having a bottom formed by the recessed portion.
Moreover, another exemplary aspect of the present invention provides a semiconductor device including the aforementioned MOS transistor.
Furthermore, another exemplary aspect of the present invention provides a method of manufacturing the aforementioned MOS transistor.
According to another exemplary aspect of the present invention, a parasitic resistance of a source and a drain is reduced in a MOS transistor. As a result, an on-state current Ion of the MOS transistor can be improved.
The above and other objects, features, and advantages of the present invention will be apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred exemplary embodiments of the present invention by way of example.
Patent Application
20080048275
