Multi chip package and related method

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described herein with reference to the accompanying drawings. In the drawings:

FIG. 1 is a block diagram of a conventional Multi Chip Package (MCP);

FIG. 2 is a block diagram of an MCP in accordance with an embodiment of the invention; and,

FIG. 3 is a flowchart illustrating a method for enabling a cell disposed in an MCP in accordance with an embodiment of the invention.

1. A multi chip package comprising: a first memory device; and,a second memory device storing repair address information about the first memory device.
2. The multi chip package of claim 1, wherein the first memory device comprises a latch adapted to store the repair address information read from the second memory device.
3. The multi chip package of claim 1, wherein the first memory device is a volatile memory device.
4. The multi chip package of claim 1, wherein the second memory device is a nonvolatile memory device.
5. The multi chip package of claim 1, wherein the second memory is an electrically erasable programmable read only memory (EEPROM) device or a flash memory device.
6. A method for enabling a cell in a multi chip package comprising a first memory device and a second memory device storing repair address information about the first memory device, the method comprising: determining whether a first address is a repair address, wherein the first address is an address of a normal cell disposed in the first memory device;reading the repair address information from the second memory device when the first address is a repair address; and,enabling a redundancy cell in the first memory device in accordance with the repair address information when the first address is a repair address.
7. The method of claim 6, further comprising: enabling the normal cell when the first address is not a repair address.

Number	Date	Country	Kind
2006-12733	Feb 2006	KR	national