The present invention relates to a computer memory. More particularly, the present invention relates to a multi function memory module.
Computers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of a computer. Sockets on a main board accommodate those memory modules also known as Single Inline Memory Modules (SIMMs) or Dual Inline Memory Modules (DIMMs). With the ever-increasing need for faster computer systems, memory devices have undergone through many architectural arrangements. For illustration purposes, the following are examples of different types of memory technology: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Fast Cycle Random Access Memory (FCRAM), and Reduced Latency Dynamic Random Access Memory (RLDRAM).
Unfortunately, system architectures also vary with the type of memory devices used. The arrangement of the circuitry on the memory module needs to match the architecture on the main board of the system. In particular, the controller and memory socket of a computing system must be compatible with the type of memory used in the system.
Thus, for example, in order to support the above three different memory technologies, a system would require three different memory modules in addition to the different memory sockets and connections supporting the different memory modules.
A need therefore exists for a single memory module to support all types of memory technologies without requiring different sockets and connections wiring for each different technology. A primary purpose of the present invention is to solve these needs and provide further, related advantages.
A memory module has a printed circuit board with connector pins. Several memory devices are mounted on the printed circuit board. An electrical circuit connects the memory devices to the connector pins such that the connector pins have multiple functionality based on the architecture of the memory devices used.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention.
In the drawings:
Embodiments of the present invention are described herein in the context of a multi-function memory module. Those of ordinary skill in the art will realize that the following detailed description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.
In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
In accordance with one embodiment of the present invention, the components, process steps, and/or data structures may be implemented using various types of operating systems (OS), computing platforms, firmware, computer programs, computer languages, and/or general-purpose machines. The method can be run as a programmed process running on processing circuitry. The processing circuitry can take the form of numerous combinations of processors and operating systems, or a stand-alone device. The process can be implemented as instructions executed by such hardware, hardware alone, or any combination thereof. The software may be stored on a program storage device readable by a machine.
In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable logic devices (FPLDs), including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein.
In accordance with one embodiment of the present invention, the method may be implemented on a data processing computer such as a personal computer, workstation computer, mainframe computer, or high performance server running an OS such as Solaris® available from Sun Microsystems, Inc. of Palo Alto, Calif., Microsoft® Windows® XP and Windows® 2000, available form Microsoft Corporation of Redmond, Wash., or various versions of the Unix operating system such as Linux available from a number of vendors. The method may also be implemented on a multiple-processor system, or in a computing environment including various peripherals such as input devices, output devices, displays, pointing devices, memories, storage devices, media interfaces for transferring data to and from the processor(s), and the like. In addition, such a computer system or computing environment may be networked locally, or over the Internet.
An electrical circuit (not shown) couples the memory devices to the connector pins 406 such that the connector pins 406 have multiple functionality based on the architecture of each memory device. Therefore, each connector pin 406 on the memory module 400 has multiple functionality, except for the power and ground pins. That is, each connector pin 406 may carry different signals based on the type of memory technology of the memory module attached to the footprints 408. An example of a configuration of the connector pins for supporting different types of memory technology (for example, DDR SDRAM, FCRAM, and RLDRAM) is described in more detail in
In accordance with another embodiment, testing pins may provide additional testing capability so that the connection module may be tested while plugged in to the main board. The testing pins may be located on the PCB 402 away from the bottom side 404 at 408. In accordance with another embodiment, the testing pins 402 may be also located along with the connector pins 406 on the bottom side 404 at 410. The testing pins may be, for example, JTAG pins. A JTAG pin out configuration in accordance with one embodiment of the present invention is discussed in more details in
For illustration purposes, the multi-function memory socket 506 may support several types of technology such as DDR SDRAM, FCRAM, and RLDRAM. Therefore, a memory module having either DDR SDRAM, FCRAM, or RLDRAM memory devices may then be coupled with the multi-function memory socket 506.
The multi-capability memory controller 504 communicates with the multi-function memory module 400 via multi-function memory socket 506. An example of a multi-capability memory controller 504 is illustrated in more detail in
Therefore, a system with a multi-function memory controller 504 capable of communicating with all of the above mentioned memory architectures may only need to communicate with one memory socket 506 on the main board to drive any of these configurations, one at a time. Thus the system 500 may be capable of communicating with a multi-function memory module that may support for example, DDR SDRAM, FCRAM, or RLDRAM memory devices. Without this approach, the system would need to have three different sockets on the board to support the different memory technologies. Those of ordinary skill in the art will appreciate that the configuration of the multi-function memory module is not intended to be limiting to the above mentioned memory technology and that other memory technology can be used without departing from the inventive concepts herein disclosed. For example, other memory technology derived from the above examples may be used such as FCRAM III or RLDRAM II.
In accordance with another embodiment, a JTAG pin out in the above multi-function memory module may provide additional testing capability so that the connection module may be tested while plugged in to the main board. The JTAG pin out configuration is discussed in more details in
In accordance with one embodiment of the present invention, the multi-function controller 604 may be able to communicate with several types of memory devices such as DDR SDRAM, FCRAM, or RLDRAM. The multi-function controller 604 may include a DDR controller 620, a FCRAM controller 622, and a RLDRAM controller 624. Each controller 620, 622, and 624 may communicate with the processor 602 via the address bus 608, control bus 610, and data bus 612. A Finite State Machine (FSM) 626 interfaces between the signals from the address bus 608, control bus 610, data bus 612 and the signals with the memory socket 606 through multiplexors 628, 630, and 632. A first multiplexor 628 channels address signals to the address bus 614 depending on the type of memory device technology (for example, DDR address, FCRAM address, or RLDRAM address). A second multiplexor 630 channels signals to the control bus 616 depending on the type of memory device technology (for example, DDR control, FCRAM control, RLDRAM control). A third multiplexor 632 channels signals to the data bus 618 depending on the type of memory device technology (for example, DDR data, FCRAM data, RLDRAM data). Those of ordinary skill in the art will appreciate that the configuration of the multi-function memory controller shown above is not intended to be limiting and that other configurations can be used without departing from the inventive concepts herein disclosed.
The following is a table of abbreviations used in
VREF=Reference Voltage
VSS=Ground
VDD=Voltage
DQx=Data line x
DQSx#=Data Strobe line x
CKx=Clock positive
CKx#=Clock negative
DMx=Data Mask
CBx=ECC Data line x
ECC=Error Correction Circuitry
CBS=CB Strobe line positive
CBS#=CB Strobe line negative
KEY=Module key location for socket insertion
NC=No Connect
RCx=Register Configuration Pin
CKEx=Clock Enable
Ax=Address
BAx=Internal Bank Address
CDM=Check-bit Data Mask
RAS#=Row Address Strobe
CAS#=Column Address Strobe
WE#=Write Enable
CSx#=Chip Select Signal
ODTx=On-Die termination
SDA=Serial Data Signal for EEPROM
SAx=Serial Address line
SCL=Serial Clock
VDDSPD=SPD Clock
SPD=Serial Presence Detect
QSx=Data Mask Strobe
DSx=Data Strobe
CQS=Check-bit Mask Strobe
PDx#=Power Down Control
CDS=Check-bit Data Strobe
FN#=Function Control
DVLD=Data Valid
REF#=Auto Refresh
AS#=Address Strobe
As an example, pin 101 on the memory module carries the CKE0 signal when it is configured for DDR SDRAM. The same pin 101 may also carry signal A18 when it is configured as RLDRAM, and signal PD0# when is it configured as FCRAM. The table in
In accordance with one embodiment of the present invention, the above illustrated pin configuration may be derived from a standard DDR II connector pin configuration. One advantage of having the pin configuration derived from a standard DDR II pin configuration is that the memory module with the above pin configuration would be compatible with a standard DDR II pinout.
In accordance with another embodiment of the present invention, the memory module may incorporate other memory technologies such as FCRAM or RLDRAM. For example, a memory module incorporating FCRAM technology would require a controller compatible with FCRAM settings.
For illustration purposes, the multi-function memory socket 906 may support several types of technology such as DDR SDRAM, FCRAM, and RLDRAM. Therefore, a memory module having either DDR SDRAM, FCRAM, or RLDRAM memory devices may then be coupled with the multi-function memory socket 906.
The multi-capability memory controller 904 communicates with the multi-function memory module 400 via multi-function memory socket 906. An example of a multi-capability memory controller 904 is illustrated in more detail in
Therefore, a system with a multi-function memory controller 904 capable of communicating with all of the above mentioned memory architectures may only need to communicate with one memory socket 906 on the main board to drive any of these configurations, one at a time. Thus the system 900 may be capable of communicating with a multi-function memory module that may support for example, DDR SDRAM, FCRAM, or RLDRAM memory devices. Without this approach, the system would need to have three different sockets on the board to support the different memory technologies. Those of ordinary skill in the art will appreciate that the configuration of the multi-function memory module is not intended to be limiting to the above mentioned memory technology and that other memory technology can be used without departing from the inventive concepts herein disclosed.
The following is a table of abbreviations in
TDI=Test Data IN
TDO=Test Data OUT
TMS=Test Mode Select
Treset=Test Reset (optional)
TCLK=Test Clock
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.