Patent Grant
8730726
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
Generally, non-volatile memory devices may have various designs. One example of an NVM cell design is the so-called SONOS (silicon-oxide-nitride-oxide-silicon) device, which may use a thin tunnel oxide layer, to allow hole direct tunneling erase operations. Although such designs may have good erase speed, the data retention is usually poor, in part because direct tunneling may occur even at a low electrical field strengths that may exist during a retention state of a memory device.
Another NVM design is NROM (nitrided read-only memory), which uses a thicker tunnel oxide layer to prevent charge loss during retention states. However, a thick tunnel oxide layer may impact channel erase speed. As a result, band-to-band tunneling hot-hole (BTBTHH) erase methods can be used to inject hole traps to compensate the electrons. However, the BTBTHH erase methods may cause some reliability issues. For example, the characteristics of NROM devices employing BTBTHH erase methods may degrade after numerous P/E (program/erase) cycles.
Thus, a need in the art exists for non-volatile memory cell designs and arrays which can be operated (programmed/erased/read) numerous times with improved data retention performance and increased operation speeds.
The present invention relates to non-volatile memory devices, and more specifically, to non-volatile memory devices including a tunnel dielectric structure that facilitates self-converging erase operations while also maintaining charge retention in a charge storage layer of the memory device during retention states.
One embodiment of the present invention includes memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer.
Another embodiment of the present invention includes memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a multi-layer tunnel dielectric structure disposed above the channel region, the multi-layer tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the multi-layer tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer.
In certain preferred embodiments, the layer providing a small hole-tunneling-barrier height may contain materials such as silicon nitride (Si3N4) or hafnium oxide (HfO2). In certain preferred embodiments of the present invention memory cells include a tunnel dielectric structure having multiple layers, such as a stacked dielectric tri-layer structure of silicon oxide, silicon nitride, and silicon oxide (ONO). Such tunnel dielectric structures provide a SONONOS (silicon-oxide-nitride-oxide-nitride-oxide-silicon) or a super-lattice SONONOS design.
In certain preferred embodiments of the present invention the tunnel dielectric structure can comprise at least two dielectric layers each having a thickness of up to about 4 nm. Additionally, in certain preferred embodiments of the present invention, the gate electrode comprises a material having a work function value greater than that of N+ polysilicon.
In certain preferred embodiments, the tunnel dielectric structure can include a layer comprising a material having a small hole tunneling barrier height, wherein the material is present in the layer at a concentration gradient such that the concentration of the material is at a maximum at a depth point within the layer.
The present invention also includes non-volatile memory devices which comprise a plurality of memory cells (i.e., an array) in accordance with one or more of the embodiments described herein. As used herein, a “plurality” refers to two or more. Memory devices in accordance with the present invention exhibit significantly improved operational properties including increased erase speeds, improved charge retention and larger windows of operation.
The present invention also includes methods of operating non-volatile memory cells and arrays. Methods of operation in accordance with the present invention include resetting the memory devices by applying a self-converging method to tighten Vt distribution of the memory devices; programming at least one of the memory devices by channel +FN injection; and reading at least one of the memory devices by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices. As used herein, the term “tighten” refers to the narrowing of the threshold voltage distribution among the many memory cells of an array. In general, threshold voltage distribution is “tightened” where the threshold voltages of several cells are within a narrow range of one another such that operation of the array is improved over conventional designs. For example, in some preferred embodiments, such as in a NAND array comprising memory cells in accordance with one or more embodiments of the present invention, a “tightened” threshold voltage distribution indicates that the threshold voltages of the various memory cells are within a 0.5V range of one another. In other array architectures employing memory cells in accordance with the present invention, the “tightened” threshold voltage distribution may have a range of about 1.0V from the upper limit to the lower limit.
One embodiment of a method of operation in accordance with the present invention includes operating an array in accordance with the present invention by applying self-converging reset/erase voltages to the substrate and the gate electrode in each memory cell to be reset/erased; programming at least one of the plurality of memory cells; and reading at least one of the plurality of memory cells by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices.
The present invention also includes methods of forming a memory cell, comprising: providing a semiconductor substrate having a source region and a drain region formed therein below a surface of the substrate and separated by a channel region; forming a tunnel dielectric structure above the channel region, wherein forming the tunnel dielectric structure comprises forming at least two dielectric layers, wherein one of the at least two dielectric layers has a smaller hole tunneling barrier height than the other of the at least two dielectric layers; forming a charge storage layer above the tunnel dielectric structure; forming an insulating layer above the charge storage layer; and forming a gate electrode above the insulating layer.
As used herein, the phrase “small hole tunneling barrier height” refers generally to values which are less than the approximate hole tunneling barrier height of silicon dioxide. In particular, a small hole tunneling barrier height is preferably less than about 4.5 eV. More preferably, a small hole tunneling barrier height is less than or equal to about 1.9 eV.
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
In the drawings:
a and 1b are cross-sectional schematic representations of an N-channel memory cell in accordance with one embodiment of the present invention and a P-channel memory cell in accordance with one embodiment of the present invention, respectively;
a-5e are band energy diagrams of ONO tunnel dielectric structures in accordance with various embodiments of the present invention;
a is a graphical representation of the threshold voltage over time of a memory cell in accordance with one embodiment of the present invention during erase after various types of programming;
b is a graphical representation of the threshold voltage over time of a memory cell having a platinum gate in accordance with one embodiment of the present invention during erase;
c and 7d are graphical representations of capacitance versus voltage for the memory cell referred to in
a and 12b are an equivalent circuit diagram and layout view, respectively, of a virtual ground array of memory cells in accordance with one embodiment of the present invention;
a and 14b are equivalent circuit diagrams of memory arrays comprising memory cells in accordance with one embodiment of the present invention and depicting suitable reset/erase voltages in accordance with two embodiments of operation in accordance with the present invention;
a and 15b are equivalent circuit diagrams of memory arrays comprising memory cells in accordance with one embodiment of the present invention depicting one method of programming in accordance with the present invention;
a and 16b are equivalent circuit diagrams of memory arrays comprising memory cells in accordance with one embodiment of the present invention depicting one method of reading a bit in accordance with the present invention;
a and 19b are graphical representations of the current at the drain of a memory cell in accordance with one embodiment under various gate voltages depicted in a logarithmic scale and a linear scale, respectively;
a and 21b are a layout view and equivalent circuit diagram of a virtual ground array in accordance with one embodiment of the present invention;
a and 22b are an equivalent circuit diagram and layout view, respectively, of a NAND array of memory cells in accordance with one embodiment of the present invention;
a and 23b are cross-sectional schematic representations of a NAND array of memory cells in accordance with one embodiment of the present invention taken along lines 22A-22A and 22B-22B, respectively, as shown in
a is an equivalent circuit diagram of a NAND array in accordance with one embodiment of the present invention depicting one method of operation in accordance with the present invention;
b is a graphical representation of threshold voltages over time during a reset operation in accordance with one embodiment of the present invention for two memory cells having different initial threshold voltages;
a and 29b are graphical representations of the current at the drain of a memory cell in accordance with one embodiment under various gate voltages at three different cycle numbers depicted in a logarithmic scale and a linear scale, respectively
Reference will now be made in detail to the invention and the presently preferred embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of entire integrated circuits. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are known in the art or to be developed.
Memory cells in accordance with the present invention can overcome some of the reliability issues in SONOS and NROM devices. For example, memory cell structures in accordance with the present invention may allow fast FN channel erase methods, while at the same time, maintaining good charge retention characteristics. Various embodiments of the memory cells according to the present invention can also alleviate reliance on the BTBTHH erase method, thereby avoiding device degradation after numerous P/E cycles.
One example may employ an ultra-thin tunnel dielectric or ultra-thin oxide layer in conjunction with the small hole tunneling barrier height layer in embodiments where the tunnel dielectric structure is a multilayer structure. This may provide better stress immunity. Non-volatile memory cells according to the present invention also show little degradation after numerous P/E cycles.
Memory cells according to the present invention may employ either an n-channel or a p-channel design, such as shown in
b depicts a cross-sectional view of an p-channel memory cell 200 in accordance with one embodiment of the present invention. The memory cell includes an n-type substrate 201 containing at least two p-doped regions 202 & 204, wherein each of the doped regions 202 & 204 may function as either a source or drain. The substrate 201 further includes a channel region 206 between the two p-doped regions. The p-channel memory cell 200 similarly includes a tunnel dielectric structure 220, comprising a tri-layer thin ONO structure wherein a small hole-tunneling-barrier height nitride layer 224 is sandwiched between a thin lower oxide layer 222 and an upper thin oxide layer 226, a charge-trapping (or charge storage) layer 230, an insulating layer 240, and a gate 250.
Thus, for example, as depicted in
Charge storage materials such as a silicon nitride layer, HfO2, and Al2O3 may be used as the small hole tunneling barrier height layer in a tunnel dielectric structure. In certain preferred embodiments of the present invention, an efficient charge storage material, such as a silicon nitride can be used as a charge storage layer in the memory device. A blocking oxide that prevents charge loss may serve as an insulating layer, such as a third silicon oxide layer O3. The memory cells according to the present invention also include a gate or gate electrode, such as a polysilicon gate, above the insulating layer. The tunnel dielectric structure, charge storage layer, insulating layer and gate can be formed above the substrate above at least a portion of a channel region, which is defined by and is disposed between a source region and a drain region.
Memory cells according to various embodiments of the present invention comprise a tunnel dielectric structure which can provide fast FN erase speeds of around 10 msec under a negative gate voltage (Vg), such as a Vg of about −10 to about −20 V. On the other hand, the charge retention can still be maintained, and, in some examples, may be better than many conventional SONOS devices. Memory cells according to the present invention can also avoid the use of band-to-band hot hole erase operations, which, are commonly used in NROM devices. Avoidance of such band-to-band hot hole erase operations may greatly eliminate hot-hole introduced damages and such avoidance is therefore desirable.
Referring to
a and 5b are band diagrams which illustrate possible effects of using a tunnel dielectric structure containing at least one layer having a small hole-tunneling-barrier height. The band diagram of the tunnel dielectric structure, an O1/N1/O2 trilayer in this example, under a low electrical field, which may exist during memory data retention, is shown in
c and 5d illustrate another set of band diagrams in one example. For a better band offset condition in one example, the thickness of N1 may be larger than that of O1. The band diagram of valence band is plotted at the same electrical field E01=14 MV/cm. The tunneling probability according to WKB approximation is correlated to the shadow area. In this example, for N1=O1 in thickness, the band offset does not completely screen out the barrier of O2. On the other hand, for N1>O1, the band offset can more easily screen out O1. Therefore, for N1>O1 in thickness, the hole tunneling current may be larger under the same electrical field in O1.
An experiment with measured and simulated hole tunneling currents, as shown in
Memory cell designs in accordance with the present invention may be applied to various memory types, including but not limited to, NOR and/or NAND-type flash memories.
As noted above, a tunnel dielectric layer may include two or more layers, including one layer that may provide a small hole-tunneling-barrier height. In one example, the layer providing a small hole-tunneling-barrier height may contain silicon nitride. The layer may be sandwiched between two silicon oxide layers, thereby forming an O/N/O tunnel dielectric if silicon nitride is used as the intermediate layer. In certain preferred embodiments of the present invention, each layer in a tunnel dielectric structure is up to about 4 nm thick. In some preferred embodiments, each of the layers in the tunnel dielectric structure can have a thickness of about 1 nm to 3 nm. In one exemplary device, a tri-layer structure may have a bottom layer, such as a silicon oxide layer, of about 10 Å to 30 Å, an intermediate layer, such as a silicon nitride layer, of about 10 Å to 30 Å, and a top layer, such as another silicon oxide layer, of about 10 Å to 30 Å. In one particular example, an O/N/O tri-layer structure having a 15 Å bottom silicon oxide layer, a 20 Å intermediate silicon nitride layer, and an 18 Å top silicon oxide layer may be used.
In one example, a thin O/N/O tri-layer structure shows negligible charge trapping. Theoretical band diagram and tunneling current analysis, such as described with reference to
In certain preferred embodiments, the tunnel dielectric structure includes at least a middle layer and two adjacent layers on opposing sides of the middle layer, wherein each of the middle layer and two adjacent layers comprises a first material and a second material, wherein the second material has a valence band energy level greater than the valence band energy level of the first material and the second material has a conduction band energy level less than the conduction band energy level of the first material; and wherein the concentration of the second material is higher in the middle layer than in the two adjacent layers and the concentration of the first material is higher in the two adjacent layers than in the middle layer. Preferably, in a tunnel dielectric structure in accordance with this embodiment of the present invention, the first material comprises oxygen and/or an oxygen-containing compound and the second material comprises nitrogen and/or a nitrogen-containing compound. For example, the first material can comprise an oxide, such as silicon oxide, and the second material can comprise a nitride, such as Si3N4 or SixOyNz.
Tunnel dielectrics in accordance with this aspect of the invention may be comprised of three or more layers, all of which can contain similar elements (such as Si, N and O), so long as the concentration of the material having the smallest hole tunneling barrier height is higher within the middle layer than in the two adjacent layers.
In certain tunnel dielectric structures according to the preceding embodiment of the present invention, the second material can be present in the middle layer in a gradient concentration such that the concentration of the second material in the middle layer increases from one adjacent layer/middle layer interface to a maximum concentration at a depth point within the middle layer, and decreases from the maximum concentration depth point to a lower concentration at the other adjacent layer/middle layer interface. The increase and decrease in concentration is preferably gradual.
In still other embodiments of the present invention, the tunnel dielectric structure includes at least a middle layer and two adjacent layers on opposing sides of the middle layer, wherein the two adjacent layers comprise a first material and the middle layer comprises a second material, wherein the second material has a valence band energy level greater than the valence band energy level of the first material and the second material has a conduction band energy level less than the conduction band energy level of the first material; and wherein the second material is present in the middle layer in a gradient concentration such that the concentration of the second material in the middle layer increases from one adjacent layer/middle layer interface to a maximum concentration at a depth point within the middle layer, and decreases from the maximum concentration depth point to a lower concentration at the other adjacent layer/middle layer interface. The increase and decrease in concentration is preferably gradual. Preferably, in a tunnel dielectric structure in accordance with this embodiment of the present invention, the first material comprises oxygen and/or an oxygen-containing compound and the second material comprises nitrogen and/or a nitrogen-containing compound. For example, the first material can comprise an oxide, such as silicon oxide, and the second material can comprise a nitride, such as Si3N4 or SixOyNz.
For example, in embodiments of the present invention where the tunnel dielectric layer comprises a tri-layer ONO structure, the bottom oxide and top oxide layers can comprise silicon dioxide and the middle nitride layer can be comprised of, for example, silicon oxynitride and silicon nitride wherein the concentration of silicon nitride (i.e., the material having the smaller hole tunneling barrier height of the two) is not constant within the layer, but rather reaches a maximum at some depth point within the layer between the two interfaces with the sandwiching oxide layers.
The precise point within the middle layer where the material with the smallest hole tunneling barrier height reaches its maximum concentration is not critical, so long as it is present in a gradient and reaches its maximum concentration in the tunnel dielectric layer at some point within the middle layer.
The gradient concentration of the material having the smallest hole tunneling barrier height can be advantageous in improving various properties of non-volatile memory devices, particularly those having a SONONOS, or SONONOS-like structure. For example, retention state charge loss can be diminished, hole tunneling under high electric fields can be improved and, to the extent it may occur, charge-trapping in the tunnel dielectric can be avoided.
The band diagram of a tunnel dielectric layer can be advantageously modified in accordance with this aspect of the present invention such that the valence band energy level and the conduction band energy level of the middle layer do not have a constant value, but rather vary across the thickness of the layer with the concentration of the material having the smallest hole tunneling barrier height. Referring to
Multi-layer tunnel dielectric structures in accordance with such embodiments of the present invention, can be prepared in a variety of ways. For example, a first silicon dioxide or silicon oxynitride layer can be formed using any number of conventional oxidation approaches including, but not limited to thermal oxidation, radical (ISSG) oxidation, and plasma oxidation/nitridation, as well as chemical vapor deposition processes. A middle layer with a gradient concentration of SiN can then be formed, for example, via chemical vapor deposition processes, or alternatively, by plasma nitridation of excess oxide or oxynitride formed on top of the first layer. A third layer, the upper oxide layer, can then be formed, for example, by oxidation or chemical vapor deposition.
A charge storage layer can then be formed over the tunnel dielectric structure. In one example, a charge storage layer of about 5 nm to 10 nm may be formed over the tunnel dielectric structure. In one particular example, a silicon nitride layer of about 7 nm or thicker may be used. The insulating layer above the charge storage layer may be about 5 nm to 12 nm. For example, a silicon oxide layer of about 9 nm or thicker may be used. And the silicon oxide layer may be formed by a thermal process converting at least a portion of a nitride layer to form the silicon oxide layer. Any method, known or to be developed, for forming layers of suitable materials described herein can be used to deposit or form tunnel dielectric layers, charge-storage layers and/or insulating layers. Suitable methods include, for example, thermal growth methods and chemical vapor deposition methods.
In one example, a thermal conversion process may provide a high density or concentration of interfacial traps that can enhance the trapping efficiency of a memory device. For example, thermal conversion of nitride can be carried out at 1000° C., while the gate flow ratio is H2:O2=1000:4000 sccm.
In addition, because silicon nitride generally has very low (about 1.9 eV) hole barrier, it may become transparent to hole tunneling under high field. Meanwhile, the total thickness of a tunnel dielectric, such as an ONO structure, may prevent direct tunneling of electrons under a low electric field. In one example, this asymmetrical behavior may provide a memory device offering not only fast hole-tunneling erase, but also reduction or elimination of charge leakage during retention.
An exemplary device may be fabricated by 0.12 μm NROM/NBit technologies. Table 1 shows the device structure and parameters in one example. The proposed tunnel dielectric with an ultra-thin O/N/O may alter the hole tunneling current. A thicker (7 nm) N2 layer may serve as a charge-trapping layer and an O3 (9 nm) layer may serve as the blocking layer in one example. Both N2 and O3 may be fabricated using NROM/NBit technologies.
In certain embodiments of the present invention, a gate can comprise a material having a work function greater than that of N′ polysilicon. In certain preferred embodiments of the present invention, such a high work function gate material can comprise a metal such as, for example, platinum, iridium, tungsten, and other noble metals. Preferably, the gate material in such embodiments has a work function greater than or equal to about 4.5 eV. In particularly preferred embodiments, the gate material comprises a high work function metal such as, for example, platinum or iridium. Additionally, preferred high work function materials include, but are not limited to P+ polysilicon, and metal nitrides such as, for example, titanium nitride and tantalum nitride. In particularly preferred embodiments of the present invention, the gate material comprises platinum.
An exemplary device in accordance with an embodiment of the present invention having a high work function gate material may also be fabricated by 0.12 μm NROM/NBit technologies. Table 2 shows the device structure and parameters in one example. The proposed tunnel dielectric with an ultra-thin O/N/O may alter the hole tunneling current. A thicker (7 nm) N2 layer may serve as a charge-trapping layer and an O3 (9 nm) layer may serve as the blocking layer in one example. Both N2 and O3 may be fabricated using NROM/NBit technologies.
Memory cells in accordance with high work function gate material embodiments of the present invention exhibit erase properties which are even more improved over other embodiments. High work function gate materials suppress gate electron injection into the trapping layer. In certain embodiments of the present invention wherein the memory cells comprise an N+ polysilicon gate, hole tunneling into the charge-trapping layer during erase occurs simultaneously with gate electron injection. This self-converging erase effect results in higher threshold voltage levels in the erased state, which can be undesirable in NAND applications. Memory cells in accordance with high work function gate material embodiments of the present invention can be used in various type of memory applications including, for example, NOR- and NAND-type memories. However, the memory cells according to high work function gate material embodiments of the present invention are particularly suitable for use in NAND applications where elevated threshold voltages in the erased/reset state can be undesirable. Memory cells in accordance with high work function gate material embodiments of the present invention can be erased via hole tunneling methods and preferably via −FN erasing operations.
An exemplary device having an ONO tunneling dielectric and an N+ polysilicon gate may be programmed by conventional SONOS or NROM method and erased by channel FN hole tunneling.
In accordance with certain embodiments of memory cells of the present invention having high work function gate materials, wherein the high work function gate suppresses gate electron injection, the threshold voltage of the device in an erased or reset state can be much lower, and even negative, depending upon erase time. The threshold voltage values of a memory device in accordance with one embodiment of the present invention wherein the gate is comprised of platinum and the tunnel dielectric layer comprises a 15/20/18 angstrom ONO structure are shown in
Moreover, retention properties of memory devices in accordance with high work function gate material embodiments the present invention are improved. The retention properties of a memory device having a platinum gate are shown in
Memory cells in accordance with various embodiments of the present invention may be operated with at least two separate schemes. For example, CHE programming with reverse read (mode 1) may be used to perform a 2-bits/cell operation. Additionally, low-power +FN programming (mode 2) may also be used for a 2-bits/cell operation. Both modes can use the same hole tunneling erase method. Mode 1 may preferably be used for a virtual ground array architecture for NOR-type flash memories. Mode 2 may preferably be used for NAND-type flash memories.
As an example,
The charge retention of an exemplary SONONOS device in accordance with one embodiment of the present invention is shown in
Accordingly, the SONONOS design identified in the above examples may provide a fast hole tunneling erase with excellent endurance properties. As noted above, the design may be implemented in both NOR and NAND-type nitride-storage flash memories. Additionally, a memory array in accordance with the present invention may include multiple memory devices with similar or different configurations.
In various embodiments of arrays according to the present invention, memory cells according to the present invention may be used in place of conventional NROM or SONOS devices in a virtual ground array architecture. The reliability problems and erase degradations may be solved or mitigated by using FN hole tunneling instead of hot-hole injection. Without limiting the scope of the invention to the specific structures described below, various operation methods in accordance with memory arrays of the present invention are described below for exemplary NOR virtual ground array architectures.
CHE or CHISEL (channel initiated secondary electron) programming and reverse read may be used for 2-bit/cell memory array. And the erase method may be a uniform channel FN hole tunneling erase. In one example, the array architecture may be a virtual ground array or a JTOX array. With reference to
a and 12b illustrate an example of a virtual ground array architecture incorporating the memory cells discussed above, such as memory cells having a tri-layer ONO tunnel dielectric. In particular,
In addition,
a and 14b illustrate possible electrical RESET schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. Before performing further P/E cycles, all the devices may first undergo an electrical “RESET”. A RESET process may ensure the Vt uniformity of memory cells in the same array and raise the device Vt to the convergent erased state. For example, applying Vg=−15 V for 1 μsec, as shown in
a and 15b illustrate programming schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. Channel hot-electron (CHE) programming may be used to program the device. For Bit-1 programming illustrated in
a and 16b illustrate reading schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. In one example, reverse read is used to read the device to perform a 2 bits/cell operation. Referring to
a and 14b also illustrate sector erase schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. In one example, sector erase with channel hole tunneling erase may applied to erase the memory cells simultaneously. An ONO tunnel dielectric in a memory cell having the SONONOS structure may offer a fast erase, which may occur in about 10 to 50 msec and a self-convergent channel erase speed. In one example, a sector erase operation condition may be similar to a RESET process. For example, referring to
Alternatively, referring to
However, the convergent Vt is also higher. This is because gate injection is more active under higher gate voltages. To reduce gate injection, P+-polysilicon gate or other metal gate with a high work function may be used alternatively as the gate material to reduce the gate-injected electrons during the erase.
a and 19b illustrate I-V characteristics during P/E cycles in one example. The corresponding I-V curves in both log scale (
a and 21b illustrate the design of a JTOX virtual ground array in one example. The JTOX virtual ground array provides an alternative implementation of using SONONOS memory cells in a memory array. In one example, one difference between the JTOX structure and a virtual ground array is that the devices in the JTOX structure that are isolated by STI processes. A typical layout example is illustrated in
As noted above, memory cell structures in accordance with the present invention are suitable for both NOR- and NAND-type flash memories. The following will describe additional examples of memory array designs and their operation methods. Without limiting the scope of the invention to the specific structures described below, various operation methods in accordance with memory arrays of the present invention are described below for exemplary NAND architectures.
As noted above, n-channel SONONOS memory devices having an ONO tunneling dielectric may be used in a memory device.
In addition to the single-block gate structure design, a split-gate array, such as a NAND array using SONONOS devices positioned between two transistor gates which are located next to the source/drain regions, may also be used. In some examples, a split-gate design may scale down device dimension to F=30 nm or below. Furthermore, the devices may be designed to obtain good reliability, to reduce or eliminate the inter-floating-gate coupling effect, or to achieve both. As discussed above, an SONONOS memory device may provide excellent self-converging erase, which may help sector-erase operations and Vt distribution control. Furthermore, a tightened erased state distribution may facilitate multi-level applications (MLC).
By using certain designs for a memory array structure, the effective channel length (Leff) may be enlarged to reduce or eliminate short-channel effects. Some examples may be designed to use no diffusion junctions, thereby avoiding the challenges in providing shallow junctions or using pocket implantations during the manufacturing processes of memory devices.
a and 22b illustrate an example of a memory array, such as an SONONOS-NAND array having memory cells in accordance with embodiment described in Table 1, with diffusion junctions. In one example, separate devices may be isolated from each other by various isolation techniques, such as by using shallow-trench isolation (STI) or the isolation technique of silicon-on-insulator (SOI). Referring to
b illustrates an exemplary layout of a memory array, such as a NAND array. Referring to
Referring again to
In some examples, the gate voltages applied to BLTs and SLTs may be less than 10 V, which may cause less gate disturb. In cases where the gate dielectric layer of BLTs and SLTs may be charged or trapped with charges, additional −Vg erase can be applied to the gates of BLT or SLT to discharge their gate dielectric layers.
Referring again to
a illustrates a cross-sectional view of an exemplary memory array, such as an SONONOS-NAND memory array, along the channel-length direction. Typically, Lg and Ls is approximately equal to F, which generally represents the critical dimension of a device (or node). The critical dimension may vary with the technologies used for fabrication. For example, F=50 nm stands for using a 50 nm node.
In examples of manufacturing a memory array, such as the arrays noted above, the processes may involve using only two primary masks or lithography processes, such as one for the polysilicon (word line) and another for STI (bit lines). In contrast, the manufacturing of NAND-type floating gate devices may require at least two-poly processing and another inter-poly ONO processing. Accordingly, the structure and manufacturing processes of the proposed devices may be simpler than those of NAND-type floating gate memories.
Referring to
In examples where STI is used of isolating separate memory devices, the trench depth of STI regions may be larger than the depletion width in p-well, especially when the junction bias used is raised higher. For example, the junction bias may be as high as about 7V for program inhibited bit line(s) (unselected bit line(s) during programming). In one example, the depth of STI regions may be in the range of about 200 to 400 nm.
After a memory array is manufactured, a reset operation may be performed to tighten the Vt distribution first before other operations of the memory array.
Generally, traditionally floating-gate devices are not capable of providing self-converging erase. In contrast, SONONOS devices may be operated with converging Reset/Erase methods. In some examples, this operation may become essential because the initial Vt distribution is often in a wide range due to certain process issues, such as process non-uniformity or plasma charging effects. The exemplary self-converging “Reset” may help to tighten, or narrow the range of, the initial Vt distribution of memory devices.
In one example of programming operations, the selected WL may be applied with a high voltage, such as a voltage of about +16 V to +20 V, to induce channel +FN injection. Other PASS gates (other unselected WL's) may be turned on to induce the inversion layer in a NAND string. +FN programming may be a low-power method in some examples. In one example, parallel programming methods such as page programming with 4K Bytes cells in parallel can burst the programming throughput to more than 10 MB/sec, while the total current consumption can be controlled within 1 mA. In some examples, to avoid program disturb in other BLs, a high voltage, such as a voltage of about 7 V may be applied to other BLs so that the inversion layer potential is raised higher to suppress the voltage drop in the unselected BLs (such as cell B in
In examples of read operations, the selected WL may be raised to a voltage that is between an erased state level (EV) and a programmed state level (PV). Other WLs may serve as the “PASS gates” so that their gate voltages may be raised a voltage higher than PV. In some examples, erase operations may be similar to the reset operation noted above, which may allow self-convergence to the same or similar reset Vt.
In particular, for cell A, which is the cell selected for programming, the voltage drop is about +18 V, which causes +FN injection. And the Vt may be raised to PV. For cell B, the voltage drop is +11 V, causing much less +FN injection, as FN injection is sensitive to Vg. For cell C, only +10 V is applied, causing no or negligible +FN injection. In some examples, a programming operation is not limited to the technique illustrated. In other words, other adequate program inhibit techniques may be applied.
a, 26, and 27 further illustrate some examples of array operations and illustrate the endurance and retention properties of some examples. As illustrated, the device degradation after a number of operation cycles may remain very small.
In some examples, the pass gate voltage for other WLs should be higher than the high-Vt state or the programmed state Vt, but not too high to trigger gate disturb. In one example, the PASS voltage is in the range of about 7 to 10 V. The applied voltage at the BL may be about 1 V. Although a larger read voltage may induce more current, the read disturb may become more apparent in some examples. In some examples, the sensing amplifier can be either placed on a source line (source sensing) or on a bit line (drain sensing).
Some examples of NAND strings may have 8, 16, or 32 memory devices per string. A larger NAND string may save more overhead and increase array efficiency. However, in some examples, the read current may be smaller and disturb may become more apparent. Therefore, adequate numbers of NAND string should be chosen based on various design, manufacture, and operation factors.
a and 29b illustrate the IV characteristics of exemplary memory devices using different scales. In particular,
In some examples, a split-gate design, such as a split-gate SONONOS-NAND design, may be used to achieve a more aggressive down-scaling of a memory array.
Referring again to
In one example, the space Ls between neighboring memory devices along the same bit line may be in the range of about 15 nm to about 30 nm. As noted above, the effective channel length may be enlarged to 2F−Ls in this example. In one example, if F is about 30 nm and Ls is about 15 nm, Leff is about 45 nm. For the operation of those exemplary memory devices, the gate voltage may be reduced to below 15 V. In addition, the inter-polysilicon voltage drop between word lines may be designed to be no larger than 7V to avoid breakdown of the spacers in the Ls spaces. In one example, this may be achieved by having an electric field of less than 5 MV/cm between neighboring word lines.
The Leff with diffusion junctions for conventional NAND floating-gate devices is about half of the their gate length. In contrast, if F is about 50 nm and Leff is about 30 nm, Leff is about 80 nm for the proposed design (the split-gate NAND) in one example. The longer Leff can provide better device characteristics by reducing or eliminating the impact of short-channel effects.
As illustrated above, a split-gate NAND design may further shrink the space (Ls) between neighboring memory cells of the same bit line. In contrast, traditional NAND-type floating-gate devices may not provide a small spacing, because inter-floating-gate coupling effect may lose the memory window The inter-floating gate coupling is the interference between adjacent memory cells when the coupling capacitance between adjacent floating gate is high (the space between the floating gates is small so that the coupling capacitance between the adjacent floating gates becomes very high such that read disturb happens). As noted above, the design may eliminate the need to fabricate certain diffusion junctions, and the inversion layer can be directly connected if all the word lines are turned on. Therefore, the design may simplify the manufacturing process of memory devices.
A multi-layer SONOS device is described using and ultra-thin ONO tunneling dielectric. With an n+ polysilicon gate, a self-convergent positive erase threshold voltage of for example about +3 V is achieved suitable for a NOR architecture, in which channel hot electron programming can be applied for storing two-bits per cell, read using the standard reverse read method, and erased with hole tunneling erase apply electric field assisted FN tunneling with a gate voltage of for example −15 volts. With a p+ polysilicon (or other high work function material) gate, a depletion mode device can be obtained having an erase threshold voltage less than zero, with a very large memory window with a program threshold voltage over about 6 volts can be achieved, suitable for NAND architecture using electric field assisted FN electron tunneling for program and electric field assisted FN hole tunneling for erase operations, with a gate voltage during erasing of for example −18 Volts.
For NAND applications, a depletion mode device (VT<0) for the erased state is desired. By using a P+-poly gate, the gate injection is reduced and the device can be erased into depletion mode as shown in
As illustrated, some examples noted above, including the structural design, array design, and operation of memory devices, may provide desirable array dimension, good reliability, good performance, or the combination of any of them. Some examples noted may be applicable for down-scaling the dimensions of non-volatile flash memories, such as NAND flash memories and flash memory for data applications. Some examples may provide SONONOS devices with uniform and self-converging channel hole-tunneling erase. Some examples also may provide good endurance of memory devices and reduce certain no hard-to-erase or over-erase issues. Also, good device characteristics, such as small degradations after P/E cycles and good charge retention, may be provided. Device uniformity within a memory array may be provided without having erratic bits or cells. Furthermore, some examples may provide good short-channel device characteristics via a split-gate NAND design, which may offer a better sense margin during the operations of the memory devices.
The foregoing disclosure of the preferred embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.
This application is a continuation of U.S. patent application Ser. No. 13/310,546 filed 2 Dec. 2011 (now U.S. Pat. No. 8,315,095), which application is a continuation of U.S. patent application Ser. No. 12/720,112 filed 9 Mar. 2010 (now U.S. Pat. No. 8,094,497), which application is a continuation of U.S. patent application Ser. No. 12/186,101 filed 5 Aug. 2008 (now U.S. Pat. No. 7,688,626), which application is a continuation of U.S. patent application Ser. No. 11/831,594 filed 31 Jul. 2007 (now U.S. Pat. No. 7,426,140), which application is a continuation of U.S. patent application Ser. No. 11/324,581 filed 3 Jan. 2006 (now U.S. Pat. No. 7,315,474), which application claims the benefit of U.S. Provisional Patent Application Nos. 60/689,314 filed 10 Jun. 2005; 60/689,231 filed 10 Jun. 2005; 60/647,012 filed 27 Jan. 2005 and 60/640,229 filed 3 Jan. 2005.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4630086 | Sato et al. | Dec 1986 | A |
| 4959812 | Momodomi et al. | Sep 1990 | A |
| 5138410 | Takebuchi | Aug 1992 | A |
| 5270969 | Iwahashi | Dec 1993 | A |
| 5278439 | Ma et al. | Jan 1994 | A |
| 5286994 | Ozawa et al. | Feb 1994 | A |
| 5295107 | Okazawa et al. | Mar 1994 | A |
| 5319229 | Shimoji et al. | Jun 1994 | A |
| 5355464 | Fandrich et al. | Oct 1994 | A |
| 5357465 | Challa | Oct 1994 | A |
| 5408115 | Chang | Apr 1995 | A |
| 5412603 | Schreck et al. | May 1995 | A |
| 5424569 | Prall | Jun 1995 | A |
| 5448517 | Iwahashi | Sep 1995 | A |
| 5483486 | Javanifard et al. | Jan 1996 | A |
| 5485422 | Bauer et al. | Jan 1996 | A |
| 5509134 | Fandrich et al. | Apr 1996 | A |
| 5515324 | Tanaka | May 1996 | A |
| 5566120 | D'Souza | Oct 1996 | A |
| 5572464 | Iwasa | Nov 1996 | A |
| 5602775 | Vo | Feb 1997 | A |
| 5644533 | Lancaster et al. | Jul 1997 | A |
| 5694356 | Wong et al. | Dec 1997 | A |
| 5745410 | Yiu et al. | Apr 1998 | A |
| 5753950 | Kojima | May 1998 | A |
| 5768192 | Eitan | Jun 1998 | A |
| RE35838 | Momodomi et al. | Jul 1998 | E |
| 5877054 | Yamauchi et al. | Mar 1999 | A |
| 5883406 | Nishizawa | Mar 1999 | A |
| 5895949 | Endoh et al. | Apr 1999 | A |
| 5952692 | Nakazato et al. | Sep 1999 | A |
| 5966603 | Eitan | Oct 1999 | A |
| 6002610 | Cong et al. | Dec 1999 | A |
| 6011725 | Eitan | Jan 2000 | A |
| 6026026 | Chan et al. | Feb 2000 | A |
| 6034896 | Ranaweera et al. | Mar 2000 | A |
| 6074917 | Chang et al. | Jun 2000 | A |
| 6096603 | Chang et al. | Aug 2000 | A |
| 6151248 | Harari et al. | Nov 2000 | A |
| 6169693 | Chan et al. | Jan 2001 | B1 |
| 6172907 | Jenne | Jan 2001 | B1 |
| 6194272 | Sung et al. | Feb 2001 | B1 |
| 6215148 | Eitan | Apr 2001 | B1 |
| 6218700 | Papadas et al. | Apr 2001 | B1 |
| 6219276 | Parker | Apr 2001 | B1 |
| 6297096 | Boaz | Oct 2001 | B1 |
| 6320786 | Chang et al. | Nov 2001 | B1 |
| 6356478 | McCollum | Mar 2002 | B1 |
| 6363013 | Lu et al. | Mar 2002 | B1 |
| 6396741 | Bloom et al. | May 2002 | B1 |
| 6436768 | Yang et al. | Aug 2002 | B1 |
| 6458642 | Yeh et al. | Oct 2002 | B1 |
| 6487114 | Jong et al. | Nov 2002 | B2 |
| 6512696 | Fan et al. | Jan 2003 | B1 |
| 6522585 | Pasternak | Feb 2003 | B2 |
| 6538923 | Parker | Mar 2003 | B1 |
| 6552386 | Wu et al. | Apr 2003 | B1 |
| 6566690 | Magri' et al. | May 2003 | B2 |
| 6566699 | Eitan | May 2003 | B2 |
| 6587903 | Roohparvar | Jul 2003 | B2 |
| 6605840 | Wu | Aug 2003 | B1 |
| 6614070 | Hirose et al. | Sep 2003 | B1 |
| 6614694 | Yeh et al. | Sep 2003 | B1 |
| 6643181 | Sofer et al. | Nov 2003 | B2 |
| 6643185 | Wang et al. | Nov 2003 | B1 |
| 6645813 | Hsieh et al. | Nov 2003 | B1 |
| 6646924 | Tsai et al. | Nov 2003 | B1 |
| 6657252 | Fried et al. | Dec 2003 | B2 |
| 6657894 | Yeh et al. | Dec 2003 | B2 |
| 6670240 | Ogura et al. | Dec 2003 | B2 |
| 6670671 | Sasago et al. | Dec 2003 | B2 |
| 6674138 | Halliyal et al. | Jan 2004 | B1 |
| 6677200 | Lee et al. | Jan 2004 | B2 |
| 6690601 | Yeh et al. | Feb 2004 | B2 |
| 6709928 | Jenne et al. | Mar 2004 | B1 |
| 6714457 | Hsu et al. | Mar 2004 | B1 |
| 6720614 | Lin et al. | Apr 2004 | B2 |
| 6720630 | Mandelman et al. | Apr 2004 | B2 |
| 6731544 | Han et al. | May 2004 | B2 |
| 6744105 | Chen et al. | Jun 2004 | B1 |
| 6753572 | Lee et al. | Jun 2004 | B2 |
| 6784480 | Bhattacharyya | Aug 2004 | B2 |
| 6794764 | Kamal et al. | Sep 2004 | B1 |
| 6795357 | Liu et al. | Sep 2004 | B1 |
| 6798012 | Ma et al. | Sep 2004 | B1 |
| 6815764 | Bae et al. | Nov 2004 | B2 |
| 6815805 | Weimer | Nov 2004 | B2 |
| 6818558 | Rathor et al. | Nov 2004 | B1 |
| 6825523 | Caprara et al. | Nov 2004 | B2 |
| 6829175 | Tsai et al. | Dec 2004 | B2 |
| 6856551 | Mokhlesi et al. | Feb 2005 | B2 |
| 6858906 | Lee et al. | Feb 2005 | B2 |
| 6881994 | Lee et al. | Apr 2005 | B2 |
| 6885044 | Ding | Apr 2005 | B2 |
| 6891262 | Nomoto et al. | May 2005 | B2 |
| 6897533 | Yang et al. | May 2005 | B1 |
| 6912163 | Zheng et al. | Jun 2005 | B2 |
| 6925007 | Harari et al. | Aug 2005 | B2 |
| 6933555 | Hsieh | Aug 2005 | B2 |
| 6936884 | Chae et al. | Aug 2005 | B2 |
| 6937511 | Hsu et al. | Aug 2005 | B2 |
| 6942320 | Chung et al. | Sep 2005 | B2 |
| 6970383 | Han et al. | Nov 2005 | B1 |
| 6977201 | Jung et al. | Dec 2005 | B2 |
| 6979857 | Forbes | Dec 2005 | B2 |
| 6995424 | Lee | Feb 2006 | B2 |
| 6996011 | Yeh et al. | Feb 2006 | B2 |
| 7005366 | Chau et al. | Feb 2006 | B2 |
| 7012297 | Bhattacharyya | Mar 2006 | B2 |
| 7015540 | Ishii et al. | Mar 2006 | B2 |
| 7018895 | Ding | Mar 2006 | B2 |
| 7026682 | Chung et al. | Apr 2006 | B2 |
| 7042045 | Kang et al. | May 2006 | B2 |
| 7049180 | Nomoto et al. | May 2006 | B2 |
| 7071061 | Pittikoun et al. | Jul 2006 | B1 |
| 7075828 | Lue et al. | Jul 2006 | B2 |
| 7106625 | Yeh | Sep 2006 | B2 |
| 7115469 | Halliyal et al. | Oct 2006 | B1 |
| 7115942 | Wang | Oct 2006 | B2 |
| 7120059 | Yeh | Oct 2006 | B2 |
| 7133313 | Shih | Nov 2006 | B2 |
| 7133316 | Lue et al. | Nov 2006 | B2 |
| 7135734 | Eldridge et al. | Nov 2006 | B2 |
| 7151692 | Wu | Dec 2006 | B2 |
| 7154143 | Jung et al. | Dec 2006 | B2 |
| 7157769 | Forbes | Jan 2007 | B2 |
| 7158420 | Lung | Jan 2007 | B2 |
| 7164603 | Shih et al. | Jan 2007 | B2 |
| 7166513 | Hsu et al. | Jan 2007 | B2 |
| 7187590 | Zous et al. | Mar 2007 | B2 |
| 7190614 | Wu | Mar 2007 | B2 |
| 7209386 | Yeh | Apr 2007 | B2 |
| 7209390 | Lue et al. | Apr 2007 | B2 |
| 7227255 | Nomoto et al. | Jun 2007 | B2 |
| 7233522 | Chen et al. | Jun 2007 | B2 |
| 7274063 | Ding | Sep 2007 | B2 |
| 7279740 | Bhattacharyya et al. | Oct 2007 | B2 |
| 7387932 | Yeh | Jun 2008 | B2 |
| 7426140 | Lue | Sep 2008 | B2 |
| 7442988 | Oh et al. | Oct 2008 | B2 |
| 7646056 | Choi et al. | Jan 2010 | B2 |
| 8315095 | Lue et al. | Nov 2012 | B2 |
| 20010012663 | Magri' et al. | Aug 2001 | A1 |
| 20020167844 | Han et al. | Nov 2002 | A1 |
| 20020179958 | Kim | Dec 2002 | A1 |
| 20030025147 | Nomoto et al. | Feb 2003 | A1 |
| 20030030100 | Lee et al. | Feb 2003 | A1 |
| 20030036250 | Lin et al. | Feb 2003 | A1 |
| 20030067032 | Caprara et al. | Apr 2003 | A1 |
| 20030146465 | Wu | Aug 2003 | A1 |
| 20030185055 | Yeh et al. | Oct 2003 | A1 |
| 20030224564 | Kang et al. | Dec 2003 | A1 |
| 20040079983 | Chae et al. | Apr 2004 | A1 |
| 20040084714 | Ishii et al. | May 2004 | A1 |
| 20040125629 | Scheuerlein et al. | Jul 2004 | A1 |
| 20040145024 | Chen et al. | Jul 2004 | A1 |
| 20040183126 | Bae et al. | Sep 2004 | A1 |
| 20040251489 | Jeon et al. | Dec 2004 | A1 |
| 20040256679 | Hu | Dec 2004 | A1 |
| 20050001258 | Forbes | Jan 2005 | A1 |
| 20050006696 | Noguchi et al. | Jan 2005 | A1 |
| 20050023603 | Eldridge et al. | Feb 2005 | A1 |
| 20050062091 | Ding | Mar 2005 | A1 |
| 20050074937 | Jung | Apr 2005 | A1 |
| 20050157549 | Mokhlesi et al. | Jul 2005 | A1 |
| 20050218522 | Nomoto et al. | Oct 2005 | A1 |
| 20050219906 | Wu | Oct 2005 | A1 |
| 20050237801 | Shih | Oct 2005 | A1 |
| 20050237809 | Shih et al. | Oct 2005 | A1 |
| 20050237813 | Zous et al. | Oct 2005 | A1 |
| 20050237815 | Lue et al. | Oct 2005 | A1 |
| 20050237816 | Lue et al. | Oct 2005 | A1 |
| 20050255652 | Nomoto et al. | Nov 2005 | A1 |
| 20050270849 | Lue | Dec 2005 | A1 |
| 20050281085 | Wu | Dec 2005 | A1 |
| 20060007732 | Yeh | Jan 2006 | A1 |
| 20060044872 | Nazarian | Mar 2006 | A1 |
| 20060088983 | Fujisawa et al. | Apr 2006 | A1 |
| 20060118858 | Jeon et al. | Jun 2006 | A1 |
| 20060186462 | Han et al. | Aug 2006 | A1 |
| 20060197145 | Pittikoun et al. | Sep 2006 | A1 |
| 20060198189 | Lue et al. | Sep 2006 | A1 |
| 20060202252 | Wang et al. | Sep 2006 | A1 |
| 20060202256 | Harari | Sep 2006 | A1 |
| 20060202261 | Lue et al. | Sep 2006 | A1 |
| 20060234446 | Wei et al. | Oct 2006 | A1 |
| 20060261401 | Bhattacharyya | Nov 2006 | A1 |
| 20060275986 | Kobayashi et al. | Dec 2006 | A1 |
| 20060281260 | Lue | Dec 2006 | A1 |
| 20070012988 | Bhattacharyya | Jan 2007 | A1 |
| 20070029625 | Lue et al. | Feb 2007 | A1 |
| 20070031999 | Ho et al. | Feb 2007 | A1 |
| 20070032018 | Tuntasood et al. | Feb 2007 | A1 |
| 20070045718 | Bhattacharyya | Mar 2007 | A1 |
| 20070069283 | Shih et al. | Mar 2007 | A1 |
| 20070076477 | Hwang et al. | Apr 2007 | A1 |
| 20070120179 | Park et al. | May 2007 | A1 |
| 20070138539 | Wu et al. | Jun 2007 | A1 |
| 20090039417 | Chen et al. | Feb 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 0016246 | Oct 1980 | EP |
| 1411555 | Apr 2004 | EP |
| 64055868 | Mar 1989 | JP |
| 05036991 | Feb 1993 | JP |
| 5258583 | Oct 1993 | JP |
| 6291332 | Oct 1994 | JP |
| 09092738 | Apr 1997 | JP |
| 09162313 | Jun 1997 | JP |
| 11040682 | Feb 1999 | JP |
| 11233653 | Aug 1999 | JP |
| 2004363329 | Dec 2004 | JP |
| 2005223198 | Aug 2005 | JP |
| 2006291332 | Oct 2006 | JP |
| 20040100740 | Dec 2004 | KR |
| 9428551 | Dec 1994 | WO |
| Entry |
|---|
| Aminzadeh et al., “Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxide-Silicon Structures under Positive Gate Bias,” IEEE Trans. on Electron Dev. 35(4) Apr. 1998 459-467. |
| Baik, Seung, et al., “High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier,” IEEE IEDM 03-545 22.3.1-22.3.4. |
| Blomme et al., “Multilayer tunneling barriers for nonvolatile memory applications,” Device Research Conf, 2002 60th DRC Digest 153-154. |
| Blomme et al., “Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric,” IEEE Trans. on Dev. and Mterials Reliability 4(3), Sep. 2004 345-351. |
| Buckley, J., et al., “Engineering of ‘Conduction Band-Crested Barriers’ or ‘Dielectric Constant-Crested Barriers’ in view of their application of floating-gate non-volatile memory devices,” VLSI 2004, 55-56. |
| Bude, J.D., et al. “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 ?m and Below,” Electron Devices Meeting, 1997. Technical Digest, International, Dec. 7-10, 1997, 279-282. |
| Chang, Kuo-Tung, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, 253-255. |
| Chindalore, et al., “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE Electron Dev. Lett 24(4) Apr. 2003, 257-259. |
| Cho, et al., “Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells,”IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, 260-262. |
| Chung, Steve S., “Low Voltage/Power and High Speed Flash Memory Technology for High Performance and Reliability,” The 3rd WIMNACT—Singapore, Oct. 15, 2003, 1-48. |
| Chung, Steve S., et al., “A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, Dec. 8-10, 2003 pp. 26.6.1-26.6.4. |
| De Blauwe, Jan, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology, vol. 1, No. 1, Mar. 2002, 72-77. |
| DiMaria, D.J., et al., “Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents,” IBM J. Res. Dev. May 1977, 227-244. |
| Eitan, Boaz, “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” SSDM, Tokyo, Japan (1999), 3 pages. |
| Eitan, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett 21(11) Nov. 2000, 543-545. |
| EPO Office Action for Application No. EP2006000000093 mailed Oct. 8, 2008, pp. 2. |
| Fujiwara, I., et al., “0.13 mm MONOS single transistor memory cell with deparated source lines,” IEDM 1998, 995-998. |
| Govoreanu et al., “An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 287-290. |
| Govoreanu et al., “Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 299-302. |
| Govoreanu et al., “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Dev. Lett. 24(2) Feb. 2003 94-10. |
| Hijiya, S., et al., “High-Speed Write/Erase EARON Cell with Graded Energy Band-Gap Insulator,” Electronics and Communications in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36. |
| Hinkle, C.L., et al., “Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers,” Surface Science, Sep. 20, 2004, vol. 566-568, 1185-1189. |
| Hirose, M., “Challenges for Future Semiconductor Development,” Microprocesses and Nanotechnology Conference, 2002. Digest of Papers. Microprocesses and Nanotechnology 2002. 2002 International, Nov. 6-8, 2002, pp. 2-3, plus 24 pages from outline. |
| Hsu et al., “Split-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming and Erase,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 78-79. |
| Huang, Chih-Jen, et al., “A Novel P-Channel Flash Electrically-Eraseble Programmable Read-Only Memory (EEPROM) Cell with Oxide-Nitride-Oxide (ONO) as Split Gate Dielectric,” Jpn. J. Appl. Phys. vol. 40, Apr. 2001, 2943-2947. |
| Huff, H.R. and Bevan, M., assemblers, “Questions at the International Workshop on Gate Insulators,” Ad Hoc Meeting on High-k Gate Dielectrics at the Semiconductor Interface Specialists Conference, Nov. 30, 2001, 3 pages. |
| Ito, et al., “A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications.” 2004 Symp. on VLSI Tech Dig. of Papers 2004, 80-81. |
| Janai, Meir, “Data Retention, Endurance and Acceleration Factors of NROM Devices,” IEEE 41st Annual International Reliability Physics Symposium, Dallas, Texas, 2003, 502-505. |
| Kim et al., “Robust Multi-Bit Programmable Flash Memory Using a Resonant Tunnel Barrier,” Electron Dev. Mtg. Dec. 5-7, 2005, IEDM Technical Digest 861-864. |
| Kobayashi, T., et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEDM 2001, 2.2.1-2.2.4. |
| Lahiri, S. K., “MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMS: A New Concept”, Physics of Semiconductor Devices, Dec. 1997, pp. 951-956, vol. 3316, No. 2. |
| Lee, Chang, et al., “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-Giga Bit Flash Memeries,” IEEE 2003, 4 pages. |
| Lee, Changhyun, et al., “A Novel Structure of SiO2/SiN/High k Dielectrics, Al2O3 for SONOS Type Flash Memory,” Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, Sep. 17-19, 2002, Nagoya, 162-163. |
| Lee, Chungho, et al., “Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals,” IEEE IEDM 03-557, 22.6.1-22.6.4. |
| Lee, Jae-Duk, et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, 264-266. |
| Likharev, “Layered Tunnel Barriers for Nonvolatile Memory Devices,” Appl. Phys. Lett. 73(15) Oct. 1998 2137-2139. |
| Liu, Zhizheng, et al., “A New Programming Technique for Flash Memory Devices,” International Symposium on VLSI Technology, Systems and Applications, Jun. 8-10, 1999, 195-198. |
| Lue et al., “A Novel P-Channel NAND-Type Flash memory with 2-bit/cell Operation and High Programming Throughput (>20 MB/sec),” IEEE 2005, 4 pages. |
| Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” IEDM Tech. Digest Dec. 2005 547-550. |
| Lue et al., U.S. Appl. No. 11/756,557 entitled “Cylindrical Channel Charge Trapping Devices With Effectively High Coupling Ratios,” filed May 31, 2007. |
| Lue, U.S. Appl. No. 11/756,559 entitled “Charge Trapping Devices With Field Distribution Layer Over Tunneling Barrier,” filed May 31, 2007. |
| Lusky, Eli et al., “Electron Discharge Model of Locally-Trapped Charge in Oxide-Nitride-Oxide (ONO) Gates for NROM Non-Volatile Semiconductor Memory Devices,” SSDM, Tokyo, Japan (Sep. 2001), 2 pages. |
| Lusky, Eli et al., “Spatial characterization of Channel hot electron injection Utilizing subthreshold slope of the localized charge storage NROM memory device,” Non-Volatile Semiconductor Memory Workshop, Monterey, CA (Aug. 2001) 2 pages. |
| Minami, et al., “New Scaling Guidelines for MNOS Nonvolatile Memory Devices,” IEEE Trans on Electron Devices 38 (11) Nov. 1991 2519-2526. |
| Naruke, K., et al., “Nonvolatile Semiconductor Memories: Technologies, design and application,” C. Hu. Ed., New York, IEEE Press, 1991, Ch. 5, pp. 183-186. |
| Office Action mailed Apr. 21, 2008 in U.S. Appl. No. 11/324,540, 22 pages. |
| Office Action mailed Nov. 23, 2007 in U.S. Appl. No. 11/197,668. |
| Office Action mailed Oct. 19, 2007 in U.S. Appl. No. 11/324,495. |
| Office Action mailed Oct. 19, 2007 in U.S. Appl. No. 11/324,540. |
| Response to Office Action mailed Apr. 21, 2008 in U.S. Appl. No. 11/324,540, filed Jul. 17, 2008, 13 pages. |
| Sasago, Y. et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s,” IEDM, 2003, pp. 823-826. |
| Search Report mailed Mar. 19, 2009 in European Application No. 06000093.2 filed on Jan. 3, 2006, 2 pages. |
| Shih et al., “A Novel 2-bit/cell Nitride Storage Flash Memory with Greater than 1M P/E-cycle Endurance,” IEEE IEDM 2004 881-884 (36.3.1-36.3.4). |
| Shin, Yoocheol, et al., “High Reliable SONOS-type NAND Flash Memory Cell with Al203 for Top Oxide,” Non-Volatile Semiconductor Memory Workshop, 2003, 2 pages. |
| Sung et al., “Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time,” IEEE Silicon Nanoelectronics Workshop Jun. 2002 83-84. |
| Takata, M., et al., “New Non-Volatile Memory with Extremely High Density Metal Nano-Dots,” IEEE IEDM 03-553, 22.5.1-22.5.4. |
| Tsai, W.J., et al., “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” Electron Devices Meeting, 2001. IEDM Technical Digest International, Dec. 2-5, 2001 pp. 32.6.1-32.6.4. |
| U.S. Appl. No. 11/394,649, filed Mar. 31, 2006, “Amendment and Response to Restriction Requirement,” filed on Oct. 12, 2007, 22 pages. |
| U.S. Appl. No. 11/394,649, filed Mar. 31, 2006, “Notice of Allowance and Fee(s) Due” mailed Feb. 15, 2008, 12 pages. |
| Walker et al., “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” 2003 Symposium on VLSI Tech Digest of Technical Papers, 29-30. |
| Wang, Tahui, et al., “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, Dec. 8-10, 2003, pp. 7.4.1-7.4.4. |
| White et al., “On the Go with SONOS” IEEE Circuits and Devices, Jul. 2000, 22-31. |
| Xuan et al., “FinFET SONOS Flash Memory for Embedded Applications,” IEEE 2003, pp. 26.4.1-26.4.4. |
| Yamada et al., “A self-convergence erasing scheme for a simple stacked gate flash EEPROM,” Proc. Int'l. Electron Devices Meeting, Dec. 1991 307-310. |
| Yeh, C.C., et al., “Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, Dec. 8-10, 2003, pp. 7.5.1-7.5.4. |
| Yeh, C.C., et al., “Phines: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEDM Tech Digest 2002, 931-934. |
| Number | Date | Country | |
|---|---|---|---|
| 20130075806 A1 | Mar 2013 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60689314 | Jun 2005 | US | |
| 60689231 | Jun 2005 | US | |
| 60647012 | Jan 2005 | US | |
| 60640229 | Jan 2005 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13310546 | Dec 2011 | US |
| Child | 13681014 | US | |
| Parent | 12720112 | Mar 2010 | US |
| Child | 13310546 | US | |
| Parent | 12186101 | Aug 2008 | US |
| Child | 12720112 | US | |
| Parent | 11831594 | Jul 2007 | US |
| Child | 12186101 | US | |
| Parent | 11324581 | Jan 2006 | US |
| Child | 11831594 | US |
