MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of embodiments will become readily apparent from the description that follows, with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional multi processor system for use in a portable communication device;

FIG. 2 is a block diagram illustrating an example of conventional multi processor system employing a memory that may be adaptable according to an embodiment;

FIG. 3 is a block diagram illustrating an internal structure of a conventional memory cell array of DRAM;

FIG. 4 is a block diagram illustrating conventional memory array portions of a multi processor system;

FIG. 5 is a block diagram of multi processor system having a multi path accessible DRAM according to embodiments;

FIG. 6 is a block diagram illustrating a layout of memory regions and ports in a multi path accessible DRAM shown in FIG. 5;

FIG. 7 is a block diagram illustrating in detail a multi path accessible DRAM of FIG. 6;

FIG. 8 is a block diagram illustrating in detail a circuit related to a datan access of shared bank shown in FIG. 7;

FIG. 9 is a circuit diagram illustrating in detail an embodiment of path deciding part shown in FIGS. 7 and 8;

FIG. 10 is a circuit diagram illustrating in detail an address multiplexer shown in FIGS. 7 and 8;

FIG. 11 is a circuit diagram illustrating in detail a second multiplexer shown in FIGS. 7 and 8;

FIG. 12 is a block diagram illustrating read and write paths shown in FIG. 8;

FIG. 13 is a block diagram illustrating a fuse option for a power source level selection per port according to embodiments;

FIG. 14 is a block diagram illustrating various control options for a power source level selection per port according to another embodiment similar to FIG. 13; and

FIG. 15 is a graph for various levels of power sources applied per port in a DRAM according to an embodiment.

Claims

1. A semiconductor memory device, comprising: a plurality of ports;a plurality of data line pairs, each port associated with one of the data line pairs;a plurality of sets of address lines, each port associated with one of the sets of address lines;a shared memory region of a memory cell array, the shared memory region accessible through the ports;an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports; and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

2. The device of claim 1, wherein the access router comprises: a row and column address multiplexer coupled to the sets of address lines and configured to select a row address and a column address from the sets of addresses for access to the shared memory region in response to the access selection signal; anda plurality of global multiplexers coupled to a global input/output line pair of the shared memory region and the data line pairs, and configured to selectively couple the global input/output line pair to one of the data line pairs in response to the access selection signal.

3. The device of claim 2, wherein the global input/output line pair of the shared memory region is accessible through every port.

4. The device of claim 2, wherein the access controller is further configured to generate the access selection signal in response to row address strobe signals, write enable signals, and bank selection addresses received through the ports.

5. The device of claim 2, further comprising: a plurality of input/output circuits, each input/output circuit coupled to an associated global multiplexer through an associated data line pair, and coupled to an associated port.

6. The device of claim 5, wherein each input/output circuit comprises: a data output path circuit including: an input/output sense amplifier coupled to the associated global multiplexer;a data multiplexer coupled to the input/output sense amplifier;a data output buffer coupled to the data multiplexer; anda data output driver coupled to the data output buffer and the associated port; anda data input path circuit including: data input buffer coupled to the associated port;a first input driver coupled to the data input buffer; anda second input driver coupled to the first input driver and the associated global multiplexer.

7. The device of claim 6, wherein at least two input/output sense amplifiers of the input/output circuits are disposed in the shared memory region.

8. The device of claim 6, wherein for each data output driver, the data output driver is configured to drive the data at a swing level determined by at least one of an associated fuse option and an associated metal option.

9. The device of claim 6, wherein a swing level of at least one data output driver is different from a swing level of at least one other data output driver.

10. The device of claim 6, wherein for each data output driver, the data output driver is configured to drive the data at a swing level determined by at least one of a mode register set command and an extended mode register set command.

11. The device of claim 2, wherein the global multiplexers are configured such that at most one global multiplexer couples the associated data input/output line pair to the global input/output line pair at any one time.

12. The device of claim 1, further comprising: a second shared memory region;a plurality of second data line pairs; anda second access router coupled to the second shared memory region, the second data line pairs, and the sets of address lines, the second access router configured to selectively couple one of the sets of address lines and one of the second data line pairs to the shared memory region in response to a second access selection signal;wherein the access controller is further configured to generate the second access selection signal in response to the control signals received through the ports.

13. The device of claim 12, wherein the access controller is further configured to allow access to the first shared memory region through the first port and access to the second shared memory region through the second port substantially simultaneously.

14. The device of claim 1, further comprising a plurality of private memory regions, each private memory region accessible only though an associated port.

15. The device of claim 1, wherein the shared memory region further comprises a plurality of memory cells, each memory cell including an access transistor and a storage capacitor.

16. A method of operating a semiconductor memory device, comprising: receiving a plurality of addresses through a plurality of ports, each address associated with an access operation through an associated port;generating a access selection signal in response to a plurality of control signals received through the ports;selecting an address from among the addresses for access to a shared memory region in response to the access selection signal;forming a data input/output path between a port associated with the selected address and the shared memory region in response to the access selection signal; andaccessing data in the shared memory region through the data input/output path.

17. The method of claim 16, wherein: selecting the address further comprises: selecting a row address from the addresses in response to the access selection signal; andselecting a column address from the addresses in response to the access selection signal; andaccessing the data in the shared memory region further comprises accessing the data in the shared memory region according to the selected row address and the selected column address.

18. The method of claim 16, wherein the shared memory region is referred to as a first shared memory region, the method further comprising: accessing data in a second shared memory region of the memory cell array through a second port substantially simultaneously as accessing the data in the first shared memory region.

19. The method of claim 16, further comprising: accessing data in a private memory region of the memory cell array through a second port substantially simultaneously as accessing the data in the shared memory region.

20. The method of claim 16, further comprising: selecting an output drive level for an output driver of a port, wherein the output drive level is different from at least one output drive level of the other ports.

21. The method of claim 16, wherein forming the data input/output path further comprises: selecting a data input/output line pair from a plurality of data input/output line pairs associated with the ports in response to the access selection signal; andcoupling a global input/output line pair of the shared memory region with the selected data input/output line pair.

22. A semiconductor memory device, comprising: at least one shared memory region of a memory cell array, each shared memory region accessible through an associated plurality of ports;for each shared memory region: an access controller coupled to the ports associated with the shared memory region and configured to generate a access selection signal in response to a plurality of control signals received through the associated ports, the access selection signal indicating a selected port that is granted access to the shared memory region;a plurality of data line pairs, each port associated with one of the data line pairs;a plurality of sets of address lines, each port associated with one of the sets of address lines;a plurality of global multiplexers coupled to a global input/output line pair of the shared memory region and the data line pairs, and configured to selectively couple the global input/output line pair to a data line pair associated with the selected port in response to the access selection signal;an address decoder coupled to column select lines and word lines of the shared memory region; andan address multiplexer coupled to the sets of address lines and an the address decoder, the address multiplexer configured to route an address on a set of address lines associated with the selected port to the address decoder in response to the access selection signal; andfor each port: at least one input/output sense amplifier and driver coupled to the associated data lines;a multiplexer and driver coupled to the input/output sense amplifier and driver; andan input/output buffer coupled to the multiplexer and driver, and coupled to the port.

23. The semiconductor memory device of claim 22, wherein: each address decoder further comprises a column decoder and a row decoder; andeach address multiplexer further comprises: a column address multiplexer coupled to the column decoder of the associated address decoder, coupled to column address lines of the associated sets of address lines, and configured to route a column address to the column decoder in response to the access selection signal; anda row address multiplexer coupled to the row decoder of the associated address decoder, coupled to row address lines of the associated sets of address lines, and configured to route a row address to the row decoder in response to the access selection signal.

24. The semiconductor memory device of claim 22, further comprising: at least one private memory region accessible through only one of the ports;for each private memory region: a global multiplexer coupled to a global input/output line pair of the private memory region and a data line pair; andan input/output sense amplifier and driver coupled to the data line pair and one of the multiplexer and drivers associated with the port.

25. The semiconductor memory device of claim 24, wherein for at least one private memory region: the input/output sense amplifier and driver is one of the input/output sense amplifiers coupled to a shared memory region accessible through the port associated with the private memory region.

26. The semiconductor memory device of claim 22, wherein: for at least one port, at least one input/output sense amplifier and driver is coupled to a plurality of the shared memory regions through the data lines associated with both the port and the shared memory regions associated with the port.